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41. 发明授权

US6037018A Shallow trench isolation filled by high density plasma chemical vapor deposition 失效
标题翻译：通过高密度等离子体化学气相沉积填充的浅沟槽隔离
公开(公告)号：US6037018A
公开(公告)日：2000-03-14
申请号：US108866
申请日：1998-07-01
申请人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Douglas Yu
发明人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Douglas Yu
IPC分类号： C23C16/40 , H01L21/762 , B05D3/06 , H01L21/76
CPC分类号： H01L21/76232 , C23C16/402
摘要： A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.
摘要翻译：用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。

42. 发明授权

US08173503B2 Fabrication of source/drain extensions with ultra-shallow junctions 有权
标题翻译：源极/漏极扩展与超浅结的制造
公开(公告)号：US08173503B2
公开(公告)日：2012-05-08
申请号：US12617955
申请日：2009-11-13
申请人： Yihang Chiu , Chu-Yun Fu
发明人： Yihang Chiu , Chu-Yun Fu
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
摘要翻译：形成集成电路器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极结构; 以及通过将选自由铟和锑组成的组中的第一元素注入到与栅极结构相邻的半导体衬底的顶部部分来执行预非晶化注入（PAI）。该方法还包括在执行PAI的步骤之后，将不同于第一元件的第二元件注入到半导体衬底的顶部。当第一元素包括铟时，第二元素包括p型元素，并且当第一元素包括锑时包括n型元素。

43. 发明授权

US07371629B2 N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications 有权
标题翻译： N / PMOS饱和电流，HCE和Vt稳定性通过接触蚀刻停止膜修改
公开(公告)号：US07371629B2
公开(公告)日：2008-05-13
申请号：US10314689
申请日：2002-12-09
申请人： Chu-Yun Fu , Chi-Hsun Hsieh , Yi-Ming Sheu , Syun-Ming Jang
发明人： Chu-Yun Fu , Chi-Hsun Hsieh , Yi-Ming Sheu , Syun-Ming Jang
IPC分类号： H01L21/8237
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/28247 , H01L21/3185 , H01L21/823814 , H01L21/823835
摘要： A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.
摘要翻译：提供了一种用于改善NMOS和PMOS晶体管中的Idsat的方法。在MOSFET制造方案中，通过PECVD技术在STI和硅化物区域和侧壁间隔物上沉积氮化硅蚀刻停止层。在氮化物上形成介电层，然后通过电介质层和氮化物层到硅化物区域制造接触孔，并填充金属。对于NMOS晶体管，硅烷和NH 3 3流速和400℃的温度对于改善NMOS短沟道Idsat至关重要。氮化物中的氢含量通过较高的NH 3和SiH 4 O 3流速而增加，但不会显着降低HCE和Vt。使用PMOS晶体管，沉积温度增加到550° C.降低氢含量，提高HCE和Vt稳定性。

44. 发明授权

US07297632B2 Scratch reduction for chemical mechanical polishing 有权
标题翻译：化学机械抛光刮刮
公开(公告)号：US07297632B2
公开(公告)日：2007-11-20
申请号：US11082517
申请日：2005-03-17
申请人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
发明人： Chuang-Ping Hou , Syun-Ming Jang , Ying-Ho Chen , Chu-Yun Fu , Tung-Ching Tseng
IPC分类号： H01L21/311
CPC分类号： H01L21/31053
摘要： A method for forming a semiconductor device utilizing a chemical-mechanical polishing (CMP) process is provided. In one example, the method includes sequentially performing a first CMP process for removing a first portion of an oxide surface of a semiconductor device using a high selectivity slurry (HSS) and a first polish pad, interrupting the first CMP process, cleaning the semiconductor device and the first polish pad, and performing a second CMP process for removing a second portion of the oxide surface.
摘要翻译：提供了一种利用化学机械抛光（CMP）工艺形成半导体器件的方法。在一个示例中，该方法包括依次执行第一CMP处理，以使用高选择性浆料（HSS）和第一抛光垫去除半导体器件的氧化物表面的第一部分，中断第一CMP工艺，清洁半导体器件和第一抛光垫，并且执行用于去除氧化物表面的第二部分的第二CMP工艺。

45. 发明授权

US07118987B2 Method of achieving improved STI gap fill with reduced stress 有权
标题翻译：实现改善STI间隙填充减少应力的方法
公开(公告)号：US07118987B2
公开(公告)日：2006-10-10
申请号：US10767657
申请日：2004-01-29
申请人： Chu-Yun Fu , Chih-Cheng Lu , Syun-Ming Jang
发明人： Chu-Yun Fu , Chih-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/76
CPC分类号： H01L21/76235 , A61F2/958 , A61F2002/9583 , A61F2250/0098 , A61M25/001 , A61M25/005 , A61M25/0054 , A61M25/0068 , A61M25/0069 , A61M25/008 , A61M25/0108 , A61M25/0127 , A61M25/1027 , A61M2025/1079 , A61M2025/1093 , A61M2205/32
摘要： A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.
摘要翻译：一种浅沟槽隔离（STI）结构及其形成方法，其具有减小的应力以改善电荷迁移率，该方法包括提供包括覆盖在半导体衬底上的至少一个图案化硬掩模层的半导体衬底; 根据所述至少一个图案化硬掩模层干蚀刻所述半导体衬底中的沟槽; 形成一个或多个衬垫层以使选自二氧化硅，氮化硅和氮氧化硅的沟槽的沟槽; 形成包含二氧化硅的一层或多层沟槽填充材料以回填沟槽; 进行至少一个热退火步骤以缓和沟槽填充材料中的累积应力; 执行CMP和干蚀刻工艺中的至少一个以去除沟槽高度上的多余沟槽填充材料; 以及去除所述至少一个图案化的硬掩模层。

46. 发明申请

US20060049036A1 Method and apparatus for real-time control and monitor of deposition processes 审中-公开
标题翻译：用于实时控制和监测沉积过程的方法和装置
公开(公告)号：US20060049036A1
公开(公告)日：2006-03-09
申请号：US10936905
申请日：2004-09-09
申请人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
发明人： Cheng-Hung Chang , Jhi-Cherng Lu , Joung-Wei Liou , Chu-Yun Fu , Weng Chang , Syung-Ming Jang
IPC分类号： C23C14/00
CPC分类号： C23C14/34 , C23C14/54
摘要： A method comprises measuring an RF voltage and ion current at a wafer during a plasma-enhanced deposition process, determining a sputter rate in response to the RF voltage and ion current measurements, detecting an abnormal condition in response to one of the RF voltage and ion current measurements, and sputter rate, and taking a corrective action in response to detecting an abnormal condition.
摘要翻译：一种方法包括在等离子体增强沉积过程期间测量晶片处的RF电压和离子电流，响应于RF电压和离子电流测量确定溅射速率，响应于RF电压和离子之一检测异常状况电流测量和溅射速率，并且响应于检测到异常状况采取校正动作。

47. 发明申请

US20050170606A1 Method of achieving improved STI gap fill with reduced stress 有权
标题翻译：实现改善STI间隙填充减少应力的方法
公开(公告)号：US20050170606A1
公开(公告)日：2005-08-04
申请号：US10767657
申请日：2004-01-29
申请人： Chu-Yun Fu , Jhi-Cherng Lu , Syun-Ming Jang
发明人： Chu-Yun Fu , Jhi-Cherng Lu , Syun-Ming Jang
IPC分类号： A61F2/00 , A61F2/84 , A61M25/00 , A61M25/10 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76235 , A61F2/958 , A61F2002/9583 , A61F2250/0098 , A61M25/001 , A61M25/005 , A61M25/0054 , A61M25/0068 , A61M25/0069 , A61M25/008 , A61M25/0108 , A61M25/0127 , A61M25/1027 , A61M2025/1079 , A61M2025/1093 , A61M2205/32
摘要： A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.
摘要翻译：一种浅沟槽隔离（STI）结构及其形成方法，其具有减小的应力以改善电荷迁移率，该方法包括提供包括覆盖在半导体衬底上的至少一个图案化硬掩模层的半导体衬底; 根据所述至少一个图案化硬掩模层干蚀刻所述半导体衬底中的沟槽; 形成一个或多个衬垫层以使选自二氧化硅，氮化硅和氮氧化硅的沟槽的沟槽; 形成包含二氧化硅的一层或多层沟槽填充材料以回填沟槽; 进行至少一个热退火步骤以缓和沟槽填充材料中的累积应力; 执行CMP和干蚀刻工艺中的至少一个以去除沟槽高度上的多余沟槽填充材料; 以及去除所述至少一个图案化的硬掩模层。

48. 发明授权

US06884736B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US06884736B2
公开(公告)日：2005-04-26
申请号：US10265937
申请日：2002-10-07
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法。半导体元件形成在基板上。半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。然后用导电材料填充接触开口以形成接触。

49. 发明授权

US06423653B1 Reduction of plasma damage for HDP-CVD PSG process 有权
标题翻译：降低HDP-CVD PSG工艺的等离子体损伤
公开(公告)号：US06423653B1
公开(公告)日：2002-07-23
申请号：US09480271
申请日：2000-01-11
申请人： Chu-Yun Fu , Syun-Ming Jang
发明人： Chu-Yun Fu , Syun-Ming Jang
IPC分类号： G01R3126
CPC分类号： H01L21/02129 , H01L21/02274 , H01L21/31053 , H01L21/31608 , H01L21/76837
摘要： A method for significantly reducing plasma damage during the deposition of inter-layer dielectric (ILD) gapfills on topographic substrates by high density plasma chemical vapor deposition (HDP-CVD). The method can also be applied to the deposition of dielectric layers on silicon oxide covered substrates. The method provides a modification of current state of the art practices in HDP-CVD by a novel variation in the RF input power to the plasma processing chamber during certain portions of the processing cycle. Specifically, top/side RF power is reduced from 3000W/4000W to 1300W/3100W during the heat-up portion of the cycle and plasma lift is eliminated during the wafer release and lift portion of the cycle by turning off the 1000W/2000W top/side RF power. A method for determining the degree of plasma induced damage by measurement of a flatband voltage is also provided.
摘要翻译：通过高密度等离子体化学气相沉积（HDP-CVD）在地形衬底上沉积层间电介质（ILD）间隙填料期间显着降低等离子体损伤的方法。该方法也可应用于在氧化硅覆盖的衬底上沉积介电层。该方法通过在处理周期的某些部分期间等离子体处理室的RF输入功率的新变化来提供HDP-CVD中现有技术现有技术的变化。具体来说，在循环的加热部分期间，顶部/侧面RF功率从3000W / 4000W降低到1300W / 3100W，通过关闭1000W / 2000W顶部/ 侧RF功率。还提供了通过测量平带电压来确定等离子体诱导的损伤程度的方法。

50. 发明授权

US06274514B1 HDP-CVD method for forming passivation layers with enhanced adhesion 有权
标题翻译：用于形成具有增强粘合力的钝化层的HDP-CVD方法
公开(公告)号：US06274514B1
公开(公告)日：2001-08-14
申请号：US09336807
申请日：1999-06-21
申请人： Syun-Ming Jang , Chu-Yun Fu
发明人： Syun-Ming Jang , Chu-Yun Fu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L2224/48095 , H01L2224/48463 , H01L2224/8592 , H01L2924/00014 , H01L2224/45099
摘要： A method for forming upon a substrate employed within a microelectronics fabrication a dielectric passivating layer with attenuated delamination and improved adhesion to subsequent passivating and encapsulating materials. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a patterned microelectronics layer. There is then formed over the substrate a silicon containing dielectric layer employing high density plasma chemical vapor deposition (IDP-CVD) in two steps, wherein the conditions of the HDP-CVD process are optimized during the second step to provide a final layer portion with a greater degree of surface topography. Subsequently there are formed over the substrate an additional passivation layer with attenuated delamination and an organic polymer overcoat layer with improved adhesion.
摘要翻译：一种用于在微电子制造中使用的基板上形成具有减弱的分层的电介质钝化层并改善对随后的钝化和封装材料的粘附性的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成图案化的微电子层。然后在两个步骤中在衬底上形成一层采用高密度等离子体化学气相沉积（IDP-CVD）的含硅电介质层，其中HDP-CVD工艺的条件在第二步骤期间被优化以提供最终层部分更大程度的表面形貌。随后，在衬底上形成具有减弱的分层的附加钝化层和具有改善的粘附性的有机聚合物外涂层。

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