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41. 发明授权

US07820508B2 Semiconductor device having capacitor and method of fabricating the same 有权
公开(公告)号：US07820508B2
公开(公告)日：2010-10-26
申请号：US11593067
申请日：2006-11-06
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Woo-Gwan Shim , Im-Soo Park
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Woo-Gwan Shim , Im-Soo Park
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/31116 , H01L27/10817 , H01L27/10852
摘要： A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.

42. 发明授权

US07781281B2 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
标题翻译：使用化学机械抛光工艺制造自对准接触垫的方法
公开(公告)号：US07781281B2
公开(公告)日：2010-08-24
申请号：US12694715
申请日：2010-01-27
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.
摘要翻译：一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层，覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

43. 发明授权

US07666789B2 Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same 有权
公开(公告)号：US07666789B2
公开(公告)日：2010-02-23
申请号：US11428925
申请日：2006-07-06
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/00
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

44. 发明申请

US20090155991A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090155991A1
公开(公告)日：2009-06-18
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译：提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

45. 发明申请

US20090025755A1 Method for treating substrate 审中-公开
标题翻译：底物处理方法
公开(公告)号：US20090025755A1
公开(公告)日：2009-01-29
申请号：US12219562
申请日：2008-07-24
申请人： Dae-Hong Eom , Chang-Ki Hong , Woo-Gwan Shim , Young-Ok Kim
发明人： Dae-Hong Eom , Chang-Ki Hong , Woo-Gwan Shim , Young-Ok Kim
IPC分类号： B08B3/10
CPC分类号： B08B3/04 , B08B3/10 , H01L21/67034 , H01L21/67051
摘要： Example embodiments relate to a method of treating a substrate after performing a cleaning step with a liquid chemical in a single substrate spin cleaner. A method of treating a substrate according to example embodiments may include forming a film of deionized water on a surface of the substrate during rinsing, and drying the substrate by supplying a drying gas to the water film on the surface of the substrate. When rinsing the substrate, the rotating speed of the substrate may be reduced to about 50 rpm or less to form a film of water on the surface of the substrate. The film of water may shield the surface of the substrate from direct exposure to atmospheric air. The film of water may be maintained on the surface of the substrate when commencing the supply of the drying gas. Consequently, the number of water marks on the dried substrate may be reduced or prevented.
摘要翻译：示例性实施方案涉及在单个底物旋转清洁剂中用液体化学品进行清洁步骤之后处理基材的方法。根据示例性实施方案的处理基材的方法可以包括在漂洗期间在基材的表面上形成去离子水膜，并通过向基材表面上的水膜供应干燥气体来干燥基材。当冲洗基板时，基板的旋转速度可以降低到约50rpm或更小，以在基板的表面上形成水膜。水膜可以屏蔽衬底表面直接暴露于大气中。当开始供应干燥气体时，水膜可以保持在基板的表面上。因此，可以减少或防止干燥的基板上的水痕的数量。

46. 发明申请

US20080164503A1 Ferroelectric Memory Devices Having a Protruding Bottom Electrode and Methods of Forming the Same 审中-公开
标题翻译：具有突起底电极的铁电存储器件及其形成方法
公开(公告)号：US20080164503A1
公开(公告)日：2008-07-10
申请号：US11970770
申请日：2008-01-08
申请人： Suk-Hun Choi , Chang-Ki Hong , Jung-Hyeon Kim , Jun-Young Lee , Jong-Heun Lim , Seong-Kyu Yun
发明人： Suk-Hun Choi , Chang-Ki Hong , Jung-Hyeon Kim , Jun-Young Lee , Jong-Heun Lim , Seong-Kyu Yun
IPC分类号： G11C11/22 , H01L29/78 , H01L21/02
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/82
摘要： A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.
摘要翻译：提供了铁电存储器件及其形成方法。形成铁电体器件包括在具有导电区域的衬底上形成绝缘层，形成与绝缘层中的导电区域电连接的底部电极，使绝缘层凹陷，并形成覆盖底部的铁电层和上电极层电极在凹陷绝缘层上方，底部电极突出在凹陷绝缘层的上表面上。

47. 发明授权

US07314578B2 Slurry compositions and CMP methods using the same 失效
标题翻译：浆料组合物和使用其的CMP方法
公开(公告)号：US07314578B2
公开(公告)日：2008-01-01
申请号：US10807139
申请日：2004-03-24
申请人： Jaekwang Choi , Jaedong Lee , Chang-Ki Hong
发明人： Jaekwang Choi , Jaedong Lee , Chang-Ki Hong
IPC分类号： C09K5/00
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/3212 , H01L21/7684
摘要： The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The slurry compositions include one or more non-ionic polymeric surfactants that will selectively form a passivation layer on an exposed polysilicon surface in order to suppress the polysilicon removal rate relative to silicon oxide and silicon nitride and improve the planarity of the polished substrate. Exemplary surfactants include alkyl and aryl alcohols of ethylene oxide (EO) and propylene oxide (PO) block copolymers and may be present in the slurry compositions in an amount of up to about 5 wt %, although much smaller concentrations may be effective. Other slurry additives may include viscosity modifiers, pH modifiers, dispersion agents, chelating agents, and amine or imine surfactants suitable for modifying the relative removal rates of silicon nitride and silicon oxide.
摘要翻译：提供适用于涉及多晶硅层的化学机械抛光（CMP）的工艺的新的浆料组合物的本发明的示例性实施方案。浆料组合物包括一种或多种非离子聚合物表面活性剂，其将在暴露的多晶硅表面上选择性地形成钝化层，以便抑制相对于氧化硅和氮化硅的多晶硅去除速率并提高抛光的基材的平面度。示例性的表面活性剂包括环氧乙烷（EO）和环氧丙烷（PO）嵌段共聚物的烷基和芳基醇，并且可以以高达约5重量％的量存在于浆料组合物中，尽管更小的浓度可能是有效的。其它浆料添加剂可以包括粘度调节剂，pH调节剂，分散剂，螯合剂和适于改变氮化硅和氧化硅的相对去除速率的胺或亚胺表面活性剂。

48. 发明申请

US20070072407A1 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
标题翻译：使用化学机械抛光工艺制造自对准接触垫的方法
公开(公告)号：US20070072407A1
公开(公告)日：2007-03-29
申请号：US11525490
申请日：2006-09-23
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.
摘要翻译：一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层，覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

49. 发明申请

US20060143993A1 Slurry compositions for use in chemical mechanical polishing and method of manufacturing semiconductor device using the same 审中-公开
标题翻译：用于化学机械抛光的浆料组合物及其制造使用其的半导体器件的制造方法
公开(公告)号：US20060143993A1
公开(公告)日：2006-07-06
申请号：US11325483
申请日：2006-01-05
申请人： Sung-Jun Kim , Chang-Ki Hong , Jae-Dong Lee , Jae-Kwang Choi
发明人： Sung-Jun Kim , Chang-Ki Hong , Jae-Dong Lee , Jae-Kwang Choi
IPC分类号： C09G1/02 , C09K3/14 , H01L21/302
CPC分类号： H01L21/3212 , C09G1/02
摘要： Slurry compositions and method used in a chemical-mechanical polishing process for manufacturing a semiconductor device may include a surfactant and a positive-ionic high molecular compound. The surfactant and the positive-ionic high molecular compound may form first and second passivation layers on the surface of an exposed polysilicon layer.
摘要翻译：用于制造半导体器件的化学机械抛光工艺中的浆料组合物和方法可以包括表面活性剂和正离子高分子化合物。表面活性剂和正离子高分子化合物可以在暴露的多晶硅层的表面上形成第一和第二钝化层。

50. 发明申请

US20050075052A1 Method and system for planarizing integrated circuit material 有权
标题翻译：用于平面化集成电路材料的方法和系统
公开(公告)号：US20050075052A1
公开(公告)日：2005-04-07
申请号：US10947458
申请日：2004-09-22
申请人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
发明人： Kwang-Bok Kim , Jae-Kwang Choi , Yong-Sun Ko , Chang-Ki Hong , Kyung-Hyun Kim , Jae-Dong Lee
IPC分类号： H01L21/304 , B24B37/04 , B24B49/16 , B24B57/02 , C09G1/02 , B24B1/00 , B24B7/19
CPC分类号： C09G1/02 , B24B37/044 , B24B49/16 , B24B57/02
摘要： For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.
摘要翻译：为了平坦化IC（集成电路）材料，使用第一浆料分配第一浆料以使IC材料的第一平面化，并且使用第二浆料分配第二浆料以进行IC材料的第二平面化。第一和第二种浆料是不同的。例如，第一浆料是二氧化硅基，用于在第一平面化期间更快的平坦化。此后，利用二氧化铈为基础，以更高的平面度进行第二平坦化，以获得IC材料的充分平坦化。

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