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41. 发明授权

US06426526B1 Single sided buried strap 失效
标题翻译：单面埋地带
公开(公告)号：US06426526B1
公开(公告)日：2002-07-30
申请号：US09870068
申请日：2001-05-30
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Gary B. Bronner , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864
摘要： An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
摘要翻译：至少部分地由位于节点导体上方的隔离套管的存在而将来自沟槽电容器装置的节点导体的容易制造的连接结构的特征在于，所述套环的至少一部分具有至少基本上保形的外表面沟槽的相邻壁的一部分，在节点导体上方的沟槽中的掩埋带区域，除了在套环的开口处之外，带区域被隔离套环侧向限定。连接结构优选地通过一种方法来形成，该方法包括在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环，同时将隔离套环留在深沟槽的其他表面。

42. 发明授权

US06348374B1 Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure 失效
标题翻译：具有垂直MOSFET和埋地位线导体结构的4F2 STC电池的工艺
公开(公告)号：US06348374B1
公开(公告)日：2002-02-19
申请号：US09597887
申请日：2000-06-19
申请人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
发明人： Satish D. Athavale , Gary B. Bronner , Ramachandra Divakaruni , Ulrike Gruening , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10885
摘要： A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.
摘要翻译：一种形成垂直晶体管的方法。在半导体衬底上形成衬垫层。通过焊盘层和半导体衬底形成槽。埋在槽中的位线形成。位线被电介质材料包围。形成延伸穿过介电材料的带，以将位线连接到半导体衬底。槽被填充在位线上方的导体。导体沿其纵向轴线切割，使得导体保持在槽的一侧。在半导体衬底之上形成基本上与位线正交的字线槽。导体的一部分在字线槽下移除，以将导体分离成单独的栅极导体。字线形成在连接到单独的栅极导体的字线槽中。

43. 发明授权

US06180972B2 Buried, implanted plate for DRAM trench storage capacitors 失效
标题翻译：埋地植入板用于DRAM沟槽存储电容器
公开(公告)号：US06180972B2
公开(公告)日：2001-01-30
申请号：US08679799
申请日：1996-07-15
申请人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
发明人： Gary B. Bronner , Wilfried Hansch , Wendell P. Noble
IPC分类号： H01L27108
CPC分类号： H01L29/66181
摘要： A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate. The structure allows biasing of the buried plate as desired, such as for reducing electrical stress on the capacitor dielectric to allow reduction in thickness thereof and reduction of area required for the trench capacitor.
摘要翻译：特别适用于形成诸如用于动态随机存取存储器中的多个沟槽电容器的公共板的掩埋板通过在晶片或半导体层的一个或多个区域中注入杂质来形成，外延生长层的半导体材料，并将注入的杂质扩散到晶片或半导体层中并进入外延层。与在电容器沟槽内提供扩散源相比，这种源的扩散避免了工艺复杂性，并且进一步提供了杂质浓度分布，随着半导体材料体内的深度而变化，导致掩埋板的明确界定和隔离掩埋板上方和下方的区域。该结构可以根据需要偏置掩埋板，例如用于减小电容器电介质上的电应力，以允许减小其厚度并减小沟槽电容器所需的面积。

44. 发明授权

US6063657A Method of forming a buried strap in a DRAM 失效
标题翻译：在DRAM中形成掩埋带的方法
公开(公告)号：US6063657A
公开(公告)日：2000-05-16
申请号：US255535
申请日：1999-02-22
申请人： Gary B. Bronner , Ramachandra Divakaruni
发明人： Gary B. Bronner , Ramachandra Divakaruni
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A method and structure for forming a buried strap in a dynamic random access memory structure. The method includes forming a trench adjacent a pass transistor of the dynamic random access memory structure, partially filling the trench with a conductor, forming a collar surrounding an upper portion of the conductor, forming a spacer in a portion of the trench above the conductor, forming an insulator in a remainder of the upper portion of the trench, forming a shallow trench isolation region on one side of the trench opposite the pass transistor, removing the spacer to form a gap between the insulator and the pass transistor, and filling the gap with a conductor to form the buried strap.
摘要翻译：一种用于在动态随机存取存储器结构中形成掩埋带的方法和结构。该方法包括在动态随机存取存储器结构的通过晶体管附近形成沟槽，用导体部分地填充沟槽，形成围绕导体的上部的环形，在导体上方的沟槽的一部分中形成间隔物，在沟槽的上部的其余部分形成绝缘体，在与沟道晶体管相对的沟槽的一侧上形成浅沟槽隔离区，去除间隔物以在绝缘体和传输晶体管之间形成间隙，并填充间隙用导体形成埋地带。

45. 发明授权

US5250829A Double well substrate plate trench DRAM cell array 失效
标题翻译：双阱衬底板沟槽DRAM单元阵列
公开(公告)号：US5250829A
公开(公告)日：1993-10-05
申请号：US818668
申请日：1992-01-09
申请人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
发明人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/02 , H01L29/78
CPC分类号： H01L27/10829
摘要： A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches.
摘要翻译：描述了高密度衬底板DRAM单元存储器件和工艺，其中与深沟槽电容器相邻形成掩埋阱区，使得DRAM转移FET的衬底区域可以与半导体衬底上的其它FET电隔离。掩埋区域通过离子注入和扩散部分形成，以与深沟槽的壁相交。

46. 发明授权

US5128271A High performance vertical bipolar transistor structure via self-aligning processing techniques 失效
标题翻译：高性能垂直双极晶体管结构通过自调心处理技术
公开(公告)号：US5128271A
公开(公告)日：1992-07-07
申请号：US608508
申请日：1990-11-02
申请人： Gary B. Bronner , David L. Harame , Mark E. Jost , Ronald N. Schulz
发明人： Gary B. Bronner , David L. Harame , Mark E. Jost , Ronald N. Schulz
IPC分类号： H01L21/285 , H01L21/331 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66242 , H01L21/28525 , H01L29/1004 , H01L29/66272 , H01L29/732 , Y10S148/01 , Y10S148/05
摘要： The present invention is a self-aligned, vertical bipolar transistor structure and a method of manufacturing such a structure. Reducing lateral dimensions with optical lithography is difficult and not much is gained without concurrently reducing alignment tolerances. For bipolar transistors the alignment tolerance is particularly important since it determines the parasitic capacitances and resistances and thus directly affects speed. In this application a new fully self-aligned transistor structure is presented that self-aligns the shallow trench, extrinsic base contact, and the emitter polysilicon to the intrinsic device area. The structure has no critical alignments. To insure extrinsic-intrinsic base linkup the intrinsic base is put in early in the process, conserved during the stack etch, and patterned underneath the sidewall during the silicon mesa etch. Unlike other mesa-like transistor structures, no out-diffusion of the extrinsic-base is required and therefore low-temperature processing can be used to maintain a narrow vertical profile.
摘要翻译：本发明是自对准的垂直双极晶体管结构和制造这种结构的方法。用光刻法减小横向尺寸是困难的，并没有同时减少对准公差的可能性。对于双极晶体管，对准公差特别重要，因为它确定寄生电容和电阻，从而直接影响速度。在这种应用中，提出了一种新的完全自对准的晶体管结构，其将浅沟槽，外部基极接触和发射极多晶硅自对准到本征器件区域。该结构没有严格的对齐。为了确保外在固有碱基连接，内在碱基被放在该过程的早期，在堆蚀刻期间保守，并且在硅台面蚀刻期间在侧壁下图案化。与其他台状晶体管结构不同，不需要外部基极的扩散，因此可以使用低温处理来保持窄的垂直分布。

47. 发明授权

US08716780B2 Three-dimensional memory array stacking structure 有权
标题翻译：三维存储阵列堆叠结构
公开(公告)号：US08716780B2
公开(公告)日：2014-05-06
申请号：US13505442
申请日：2010-08-26
申请人： Mark D. Kellam , Gary B. Bronner
发明人： Mark D. Kellam , Gary B. Bronner
IPC分类号： H01L29/76 , H01L29/788 , H01L29/66 , H01L29/06 , H01L47/00
CPC分类号： G11C5/063 , G11C5/02 , H01L27/2409 , H01L27/2418 , H01L27/2454 , H01L27/249 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146
摘要： A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
摘要翻译：存储装置包括平面基板，平面基板上方的多个水平导电平面以及与多个水平导电平面交错的多个水平绝缘层。垂直于多个导电平面和绝缘层的垂直导电柱阵列穿过多个导电平面和绝缘层中的孔。存储器件包括多个可编程存储器元件，每个可编程存储器元件将一个水平导电平面耦合到相应的垂直导电柱。

48. 发明授权

US08497544B2 Repairing defects in a nonvolatile semiconductor memory module utilizing a heating element 失效
标题翻译：利用加热元件修复非易失性半导体存储器模块中的缺陷
公开(公告)号：US08497544B2
公开(公告)日：2013-07-30
申请号：US13486977
申请日：2012-06-01
申请人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
发明人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
摘要翻译：存储器模块包括安装到基板的多个存储器件和与存储器件热接触地设置的一个或多个分立加热元件。每个存储器件包括经受操作引起的缺陷的电荷存储存储单元，其使存储器单元存储数据的能力降低。离散加热元件或单独的分立加热元件将存储器件加热到退火缺陷的温度。

49. 发明申请

US20110286280A1 Pulse Control For NonVolatile Memory 有权
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：US20110286280A1
公开(公告)日：2011-11-24
申请号：US13146521
申请日：2010-01-29
申请人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
发明人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：本公开提供了一种非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当需要改变相关联的存储器单元中的状态时，存储器单元通道和参考电压（响应于位线选择）之间的耦合是脉冲式的。每个脉冲可以选择为小于约（20）纳秒，而脉冲之间的“休止期”通常被选择为约百纳秒或更大（例如，一微秒）的数量级。由于使用位线控制，所以可以启用非常短的上升时间，能够产生（50）纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 如果需要，还可以使用分段字线或位线来最小化RC负载并且使足够短的上升时间使得脉冲变得坚固。

50. 发明授权

US07129130B2 Out of the box vertical transistor for eDRAM on SOI 失效
公开(公告)号：US07129130B2
公开(公告)日：2006-10-31
申请号：US11298800
申请日：2005-12-09
申请人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
发明人： James W. Adkisson , Gary B. Bronner , Dureseti Chidambarrao , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242 , H01L2/20
CPC分类号： H01L27/10841 , H01L27/10864 , H01L27/10867
摘要： The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diffusion region formed through a buried oxide layer. The upper strap diffusion region is formed by laterally etching a portion of the buried oxide region to produce a divot, in which doped polysilicon is deposited. The upper strap region diffusion region also provides the source for the vertical transistor of the vertical memory device. The vertical memory device may also be integrated with a support region having logic devices formed atop the silicon-on-insulator substrate.

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