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41. 发明申请

US20080104336A1 PERFORMING A MEMORY WRITE OF A DATA UNIT WITHOUT CHANGING OWNERSHIP OF THE DATA UNIT 有权
标题翻译：执行数据单元的存储器写入而不改变数据单元的所有权
公开(公告)号：US20080104336A1
公开(公告)日：2008-05-01
申请号：US11553813
申请日：2006-10-27
申请人： Blaine D. Gaither , Judson E. Veazey , Patrick Knebel
发明人： Blaine D. Gaither , Judson E. Veazey , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the second device.
摘要翻译：一种方法包括当第一设备具有数据单元的所有权时，第二设备发出执行所述数据单元的存储器写入的请求。该方法还包括执行存储器写入而不改变对第二设备的所有权的存储器控制器。

42. 发明申请

US20080086601A1 Hierarchical cache coherence directory structure 失效
标题翻译：层次缓存一致性目录结构
公开(公告)号：US20080086601A1
公开(公告)日：2008-04-10
申请号：US11544690
申请日：2006-10-06
申请人： Blaine D. Gaither , Verna Knapp
发明人： Blaine D. Gaither , Verna Knapp
IPC分类号： G06F13/28
CPC分类号： G06F12/0824
摘要： A method for maintaining cache coherence comprises coordinating operations among a plurality of processors distributed among a plurality of nodes coupled by an interconnect fabric and managing cache coherence in a plurality of memory directories respectively associated with the processor plurality in combination with a node controller directory cache associated with a node controller coupled between the processor plurality and the interconnect fabric. The method further comprises maintaining memory coherence directory information comprising identifying processors within a node in a first portion of bits of a memory directory entry coupled to an associated processor in the node and identifying subsets of processors external to the node in the system in a second portion of bits.
摘要翻译：一种用于维持高速缓存一致性的方法包括协调分配在由互连结构耦合的多个节点之间的多个处理器之间的操作，并且在多个存储器目录中分配与处理器多个存储器目录相关联的高速缓存一致性，与节点控制器目录缓存相关联其中节点控制器耦合在处理器多个和互连结构之间。该方法还包括维护存储器一致性目录信息，包括识别耦合到节点中的相关处理器的存储器目录条目的位的第一部分中的节点内的处理器，以及在第二部分中识别系统中节点外部的处理器的子集的位。

43. 发明授权

US07051195B2 Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset 有权
公开(公告)号：US07051195B2
公开(公告)日：2006-05-23
申请号：US10002971
申请日：2001-10-26
申请人： Blaine D. Gaither , Robert J Brooks
发明人： Blaine D. Gaither , Robert J Brooks
IPC分类号： G06F13/18
CPC分类号： G06F9/383 , G06F9/30145 , G06F9/3842
摘要： In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is made, based on the conditions, as to whether or not to process the request. To facilitate the invention, certain bit fields within the instruction are encoded to identify the request as speculative or not. Additional bit fields may define a priority of a speculative request to influence the decision to process as based on the conditions. CPU architectures incorporating prefetch logic may be modified to recognize instructions encoded with speculation and priority identification fields to implement the invention in existing systems. Other logic, e.g., bus controllers and switches, may similarly process speculative requests to enhance system performance.

44. 发明授权

US06950135B2 Method and apparatus for gathering three dimensional data with a digital imaging system 失效
标题翻译：用数字成像系统收集三维数据的方法和装置
公开(公告)号：US06950135B2
公开(公告)日：2005-09-27
申请号：US09768477
申请日：2001-01-24
申请人： Bret A. McKee , Blaine D. Gaither , Michael J Mahon
发明人： Bret A. McKee , Blaine D. Gaither , Michael J Mahon
IPC分类号： G01S17/10 , G01S17/89 , G03B13/18 , G06K9/00 , H01L27/00 , H04N3/14 , H04N5/225 , H04N5/353 , H04N13/00 , H04N5/335
CPC分类号： G01S17/89 , G01S17/107
摘要： A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.
摘要翻译：包括能够测量图像拍摄装置和成像对象之间的距离的电路的数字图像捕获装置允许捕获面向图像捕获装置的对象的表面的三维数据。距离数据通过添加闪光单元获得，并且对于图像捕获设备内的多个像素进行非常高分辨率的定时器来测量闪光从物体反射所需的时间。由于光速恒定，所以可以从闪光灯到达设备的延迟来计算从闪光到物体到摄像装置的距离。可以使用多个像素来构建面向图像捕获装置的物体的表面的三维模型。可以采用包括距离数据的多个图像，以便生成对象表面的完整的三维模型。

45. 发明授权

US06792550B2 Method and apparatus for providing continued operation of a multiprocessor computer system after detecting impairment of a processor cooling device 有权
标题翻译：在检测到处理器冷却装置的损坏之后提供多处理器计算机系统的持续操作的方法和装置
公开(公告)号：US06792550B2
公开(公告)日：2004-09-14
申请号：US09775404
申请日：2001-01-31
申请人： Benjamin D. Osecky , Blaine D. Gaither
发明人： Benjamin D. Osecky , Blaine D. Gaither
IPC分类号： G06F100
CPC分类号： G06F11/004 , G06F1/206 , G06F11/006 , G06F11/20 , G06F11/3006 , G06F11/3017 , G06F11/3024 , G06F11/3058 , H05K7/20836 , Y02D10/16
摘要： A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system processes are moved from the affected CPU coupled to the failing cooling device to one or more other CPUs. The system state is then altered so that interrupts are no longer received and processed by the affected CPU, and all memory caches associated with the affected CPU are flushed back to main memory to ensure cache coherency. At this point, the CPU is either powered-down, or placed in a low-power mode that allows the CPU to operate without the cooling device, while the processes that were removed from the suspended CPU continue executing on other CPUs. After the cooling device has been replaced and is operating normally, the CPU can be powered back up, interrupts can be enabled, and the CPU can once again execute user and operating system processes.
摘要翻译：在与中央处理单元（CPU）耦合的冷却装置发生故障之后，多处理器计算机系统继续运行。根据本发明，检测到冷却装置的即将发生的故障，并且将所有用户和操作系统处理从耦合到故障冷却装置的受影响的CPU移动到一个或多个其他CPU。然后更改系统状态，以便受影响的CPU不再接收和处理中断，并且与受影响的CPU相关联的所有内存缓存都将刷新到主内存，以确保高速缓存一致性。此时，CPU处于掉电状态或置于低功耗模式，允许CPU在没有冷却设备的情况下运行，而从中止CPU中删除的进程在其他CPU上继续执行。在冷却装置更换并正常运行后，CPU可以重新上电，中断可以启用，CPU可以再次执行用户和操作系统进程。

46. 发明授权

US06532151B2 Method and apparatus for clearing obstructions from computer system cooling fans 失效
公开(公告)号：US06532151B2
公开(公告)日：2003-03-11
申请号：US09775164
申请日：2001-01-31
申请人： Benjamin D. Osecky , Blaine D. Gaither
发明人： Benjamin D. Osecky , Blaine D. Gaither
IPC分类号： H05K720
CPC分类号： G06F11/004 , G06F1/206 , G06F11/20 , H05K7/20836
摘要： An obstruction is removed from a computer system cooling fan by manipulating fan rotation. When a fan obstruction is detected, the fan is stopped. If the obstruction is caused by an object that was drawn toward the fan intake, such as a sheet of paper, this operation may clear the obstruction. The fan may also be reversed to attempt to blow the obstruction clear of the fan. Thereafter, the fan is returned to normal operation and is monitored to determine whether the obstruction was removed. If the fan is still obstructed, these steps can be repeated. If the attempts to clear the obstruction are unsuccessful, then the computer system operator or management software can be signaled.

47. 发明授权

US5915114A Dynamic trace driven object code optimizer 失效
标题翻译：动态跟踪驱动的对象代码优化器
公开(公告)号：US5915114A
公开(公告)日：1999-06-22
申请号：US799950
申请日：1997-02-14
申请人： Bret A. McKee , Blaine D. Gaither
发明人： Bret A. McKee , Blaine D. Gaither
IPC分类号： G06F9/45 , G06F11/34 , G06F11/00
CPC分类号： G06F8/443 , G06F11/3466 , G06F2201/865
摘要： A dynamic trace-driven object code optimizer provides for dynamic, real-time optimization of executable object code. The dynamic trace-driven object code optimizer bases the real-time optimization of executable object code on data gathered from execution traces collected in real-time. The executable code is then modified in real-time to generate optimized object code that is able to run more quickly and efficiently on the current system.
摘要翻译：动态跟踪驱动的对象代码优化器提供可执行对象代码的动态，实时优化。动态跟踪驱动的对象代码优化器将可执行对象代码的实时优化基于从实时收集的执行跟踪收集的数据。然后可执行代码实时修改，以生成能够在当前系统上更快更有效地运行的优化目标代码。

48. 发明授权

US08688890B2 Bit ordering for communicating an address on a serial fabric 有权
标题翻译：用于在串行结构上传送地址的位排序
公开(公告)号：US08688890B2
公开(公告)日：2014-04-01
申请号：US11635316
申请日：2006-12-05
申请人： Blaine D. Gaither , Verna Knapp
发明人： Blaine D. Gaither , Verna Knapp
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0831
摘要： A method for handling a request of storage on a serial fabric comprising formatting an address for communication on a serial fabric into a plurality of fields including a field comprising at least one set selection bit and a field comprising at least one tag bit. The address is communicated on the serial fabric with the field comprising the at least one set selection bit communicated first.
摘要翻译：一种用于处理在串行结构上的存储请求的方法，包括将用于串行结构上的通信的地址格式化为多个字段，所述多个字段包括包括至少一个集合选择位的字段和包括至少一个标签位的字段。该地址在串行结构上传送，其中该字段包括首先通信的至少一个选择位。

49. 发明授权

US08683139B2 Cache and method for cache bypass functionality 有权
标题翻译：缓存和缓存旁路功能的方法
公开(公告)号：US08683139B2
公开(公告)日：2014-03-25
申请号：US11554827
申请日：2006-10-31
申请人： Blaine D. Gaither , Patrick Knebel
发明人： Blaine D. Gaither , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0804 , G06F12/0815 , G06F12/0897
摘要： A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller is configured to receive memory requests to be satisfied by the cache memory or the main memory. In addition, the cache controller is configured to process cache activity information to cause at least one of the memory requests to bypass the cache memory.
摘要翻译：提供了用于将处理器与主存储器可操作地耦合的高速缓存。高速缓存包括与高速缓冲存储器可操作地耦合的高速缓冲存储器和高速缓存控制器。缓存控制器被配置为接收由高速缓冲存储器或主存储器满足的存储器请求。此外，高速缓存控制器被配置为处理高速缓存活动信息以使至少一个存储器请求绕过高速缓冲存储器。

50. 发明申请

US20120221798A1 Computer Cache System With Stratified Replacement 有权
公开(公告)号：US20120221798A1
公开(公告)日：2012-08-30
申请号：US13464982
申请日：2012-05-05
申请人： Blaine D. Gaither
发明人： Blaine D. Gaither
IPC分类号： G06F12/12
CPC分类号： G06F12/0811 , G06F12/082 , G06F12/128
摘要： Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction.

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