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1. 发明授权

US07600079B2 Performing a memory write of a data unit without changing ownership of the data unit 有权
标题翻译：执行数据单元的存储器写入，而不改变数据单元的所有权
公开(公告)号：US07600079B2
公开(公告)日：2009-10-06
申请号：US11553813
申请日：2006-10-27
申请人： Blaine D. Gaither , Judson E. Veazey , Patrick Knebel
发明人： Blaine D. Gaither , Judson E. Veazey , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the second device.
摘要翻译：一种方法包括当第一设备具有数据单元的所有权时，第二设备发出执行所述数据单元的存储器写入的请求。该方法还包括执行存储器写入而不改变对第二设备的所有权的存储器控制器。

2. 发明申请

US20080104336A1 PERFORMING A MEMORY WRITE OF A DATA UNIT WITHOUT CHANGING OWNERSHIP OF THE DATA UNIT 有权
标题翻译：执行数据单元的存储器写入而不改变数据单元的所有权
公开(公告)号：US20080104336A1
公开(公告)日：2008-05-01
申请号：US11553813
申请日：2006-10-27
申请人： Blaine D. Gaither , Judson E. Veazey , Patrick Knebel
发明人： Blaine D. Gaither , Judson E. Veazey , Patrick Knebel
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the second device.
摘要翻译：一种方法包括当第一设备具有数据单元的所有权时，第二设备发出执行所述数据单元的存储器写入的请求。该方法还包括执行存储器写入而不改变对第二设备的所有权的存储器控制器。

3. 发明申请

US20080222343A1 MULTIPLE ADDRESS SEQUENCE CACHE PRE-FETCHING 失效
标题翻译：多地址序列高速缓存预处理
公开(公告)号：US20080222343A1
公开(公告)日：2008-09-11
申请号：US11683573
申请日：2007-03-08
申请人： Judson E. Veazey , Blaine D. Gaither
发明人： Judson E. Veazey , Blaine D. Gaither
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cache-line addresses. If the second cache-line address is adjacent to one of the first cache-line addresses, data associated with a third cache-line address adjacent to the second cache-line address is pre-fetched into the cache memory, if not already present in the cache memory.
摘要翻译：提供了一种用于将数据预取入高速缓冲存储器的方法。存储来自至少一个处理器的多个数据请求中的每一个的第一高速缓存行地址。将来自处理器的下一个数据请求的第二高速缓存行地址与第一高速缓存行地址进行比较。如果第二高速缓存行地址与第一高速缓存线地址之一相邻，则与第二高速缓存行地址相邻的与第三高速缓存行地址相关联的数据被预取到高速缓冲存储器中，如果尚未存在缓存内存。

4. 发明授权

US08051250B2 Systems and methods for pushing data 有权
标题翻译：推送数据的系统和方法
公开(公告)号：US08051250B2
公开(公告)日：2011-11-01
申请号：US11686132
申请日：2007-03-14
申请人： Blaine D Gaither , Darel N. Emmot , Judson E. Veazey , Benjamin D. Osecky
发明人： Blaine D Gaither , Darel N. Emmot , Judson E. Veazey , Benjamin D. Osecky
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0815 , G06F2212/507
摘要： A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence of the push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.
摘要翻译：一种用于推送数据的系统，系统包括存储数据块的相干副本的源节点。该系统还包括配置成确定数据块的下一个消费者的推送引擎。在没有推送引擎检测到来自下一个消费者的数据块的请求的情况下进行的确定。推送引擎使源节点将数据块推送到与下一个消费者相关联的存储器，以减少下一个消费者访问数据块的延迟。

5. 发明申请

US20080229009A1 SYSTEMS AND METHODS FOR PUSHING DATA 有权
标题翻译：用于推动数据的系统和方法
公开(公告)号：US20080229009A1
公开(公告)日：2008-09-18
申请号：US11686132
申请日：2007-03-14
申请人： Blaine D. Gaither , Darel N. Emmot , Judson E. Veazey , Benjamin D. Osecky
发明人： Blaine D. Gaither , Darel N. Emmot , Judson E. Veazey , Benjamin D. Osecky
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0813 , G06F12/0815 , G06F2212/507
摘要： A system for pushing data, the system includes a source node that stores a coherent copy of a block of data. The system also includes a push engine configured to determine a next consumer of the block of data. The determination being made in the absence oft he push engine detecting a request for the block of data from the next consumer. The push engine causes the source node to push the block of data to a memory associated with the next consumer to reduce latency of the next consumer accessing the block of data.
摘要翻译：一种用于推送数据的系统，系统包括存储数据块的相干副本的源节点。该系统还包括配置成确定数据块的下一个消费者的推送引擎。在没有推动引擎检测到来自下一个消费者的数据块的请求的情况下进行的确定。推送引擎使源节点将数据块推送到与下一个消费者相关联的存储器，以减少下一个消费者访问数据块的延迟。

6. 发明申请

US20080104332A1 CACHE MEMORY SYSTEM AND METHOD FOR PROVIDING TRANSACTIONAL MEMORY 有权
标题翻译：用于提供交易记忆的高速缓存存储器系统和方法
公开(公告)号：US20080104332A1
公开(公告)日：2008-05-01
申请号：US11554672
申请日：2006-10-31
申请人： Blaine D. Gaither , Judson E. Veazey
发明人： Blaine D. Gaither , Judson E. Veazey
IPC分类号： G06F13/28
CPC分类号： G06F12/0815 , G06F12/0822
摘要： A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.
摘要翻译：描述了提供事务性存储器的方法。高速缓存一致性协议在包括高速缓存行的高速缓存存储器中被强制执行，其中每条线路处于修改状态，归属状态，独占状态，共享状态和无效状态之一。在开始访问至少一个高速缓存行的事务时，确保每一行都被共享或无效。在事务期间，响应于修改，拥有或排除状态中任何高速缓存行的外部请求，修改或归属状态中的每一行都无效，而不将行写入主存储器。此外，每个独占行被降级为共享或无效状态，并且事务被中止。

7. 发明授权

US08924653B2 Transactional cache memory system 有权
标题翻译：事务缓存系统
公开(公告)号：US08924653B2
公开(公告)日：2014-12-30
申请号：US11554672
申请日：2006-10-31
申请人： Blaine D. Gaither , Judson E. Veazey
发明人： Blaine D. Gaither , Judson E. Veazey
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0815 , G06F12/0822
摘要： A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an owned state, an exclusive state, a shared state, and an invalid state. Upon initiation of a transaction accessing at least one of the cache lines, each of the lines is ensured to be either shared or invalid. During the transaction, in response to an external request for any cache line in the modified, owned, or exclusive state, each line in the modified or owned state is invalidated without writing the line to a main memory. Also, each exclusive line is demoted to either the shared or invalid state, and the transaction is aborted.
摘要翻译：描述了提供事务性存储器的方法。高速缓存一致性协议在包括高速缓存行的高速缓存存储器中被强制执行，其中每条线路处于修改状态，归属状态，独占状态，共享状态和无效状态之一。在开始访问至少一个高速缓存行的事务时，确保每一行都被共享或无效。在事务期间，响应于修改，拥有或排除状态中任何高速缓存行的外部请求，修改或归属状态中的每一行都无效，而不将行写入主存储器。此外，每个独占行被降级为共享或无效状态，并且事务被中止。

8. 发明授权

US07739478B2 Multiple address sequence cache pre-fetching 失效
标题翻译：多地址序列缓存预取
公开(公告)号：US07739478B2
公开(公告)日：2010-06-15
申请号：US11683573
申请日：2007-03-08
申请人： Judson E. Veazey , Blaine D. Gaither
发明人： Judson E. Veazey , Blaine D. Gaither
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cache-line addresses. If the second cache-line address is adjacent to one of the first cache-line addresses, data associated with a third cache-line address adjacent to the second cache-line address is pre-fetched into the cache memory, if not already present in the cache memory.
摘要翻译：提供了一种用于将数据预取入高速缓冲存储器的方法。存储来自至少一个处理器的多个数据请求中的每一个的第一高速缓存行地址。将来自处理器的下一个数据请求的第二高速缓存行地址与第一高速缓存行地址进行比较。如果第二高速缓存行地址与第一高速缓存线地址之一相邻，则与第二高速缓存行地址相邻的与第三高速缓存行地址相关联的数据被预取到高速缓冲存储器中，如果尚未存在缓存内存。

9. 发明授权

US06879270B1 Data compression in multiprocessor computers 有权
标题翻译：多处理器计算机中的数据压缩
公开(公告)号：US06879270B1
公开(公告)日：2005-04-12
申请号：US10644282
申请日：2003-08-20
申请人： Judson E. Veazey
发明人： Judson E. Veazey
IPC分类号： G06F15/173 , G06F13/16 , H03M7/40
CPC分类号： G06F13/1668
摘要： A compression/decompression (codec) engine is provided for use in conjunction with a fabric agent chip in a multiprocessor computer system. The fabric agent chip serves as an interface between a first memory controller on a first cell board in the computer system and other memory controllers on other cell boards in the computer system. Cell boards in the computer system are interconnected by a system fabric. Memory data read by the first memory controller is compressed by the codec engine prior to being transmitted over the system fabric by the fabric agent chip. Conversely, memory data received over the system fabric by the fabric agent chip is decompressed by the codec engine prior to being provided to the first memory controller. Other fabric agent chips in the computer system may similarly be provided with corresponding codec engines.
摘要翻译：提供压缩/解压缩（codec）引擎，用于与多处理器计算机系统中的结构代理芯片结合使用。织物代理芯片用作计算机系统中的第一单元板上的第一存储器控制器和计算机系统中其它单元板上的其它存储器控制器之间的接口。计算机系统中的单元板通过系统结构互连。由第一存储器控制器读取的存储器数据在通过结构代理芯片通过系统结构传输之前被编解码器引擎压缩。相反，在被提供给第一存储器控制器之前，结构代理芯片在系统结构上接收的存储器数据被编解码器引擎解压缩。计算机系统中的其他织物代理芯片可以类似地提供相应的编解码器引擎。

10. 发明申请

US20080104333A1 TRACKING OF HIGHER-LEVEL CACHE CONTENTS IN A LOWER-LEVEL CACHE 审中-公开
标题翻译：在较低级别的高速缓存中跟踪高级缓存内容
公开(公告)号：US20080104333A1
公开(公告)日：2008-05-01
申请号：US11554690
申请日：2006-10-31
申请人： Judson E. Veazey
发明人： Judson E. Veazey
IPC分类号： G06F13/28
CPC分类号： G06F12/0897 , G06F12/0817
摘要： A cache memory system is provided which includes a higher-level cache, a lower-level cache, and a bus coupling the higher-level cache and the lower-level cache together. Also included is a directory array coupled with the lower-level cache. The lower-level cache is configured to track all of the data contents of the higher-level cache in the directory array without duplicating the data contents in the lower-level cache.
摘要翻译：提供了一种高速缓冲存储器系统，其包括较高级别的高速缓存，较低级的高速缓存和将高级缓存和下级缓存耦合在一起的总线。还包括与下级缓存耦合的目录数组。下级缓存被配置为跟踪目录阵列中的高级缓存的所有数据内容，而不会复制下级缓存中的数据内容。

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