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1. 发明授权

US07051195B2 Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset 有权
公开(公告)号：US07051195B2
公开(公告)日：2006-05-23
申请号：US10002971
申请日：2001-10-26
申请人： Blaine D. Gaither , Robert J Brooks
发明人： Blaine D. Gaither , Robert J Brooks
IPC分类号： G06F13/18
CPC分类号： G06F9/383 , G06F9/30145 , G06F9/3842
摘要： In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is made, based on the conditions, as to whether or not to process the request. To facilitate the invention, certain bit fields within the instruction are encoded to identify the request as speculative or not. Additional bit fields may define a priority of a speculative request to influence the decision to process as based on the conditions. CPU architectures incorporating prefetch logic may be modified to recognize instructions encoded with speculation and priority identification fields to implement the invention in existing systems. Other logic, e.g., bus controllers and switches, may similarly process speculative requests to enhance system performance.

2. 发明授权

US08923073B2 Storage element reading using ring oscillator 有权
标题翻译：使用环形振荡器的存储元件读数
公开(公告)号：US08923073B2
公开(公告)日：2014-12-30
申请号：US13823826
申请日：2010-11-01
申请人： Robert J Brooks
发明人： Robert J Brooks
IPC分类号： G11C11/00 , G11C7/06 , G11C7/22 , G11C13/00 , G11C7/10 , G11C7/00
CPC分类号： G11C13/0069 , G11C7/00 , G11C7/1015 , G11C13/0004
摘要： Methods and apparatus are provided for use with data storage elements. A ring oscillator is coupled to a selected element within an array such that a feedback loop is defined. A period at oscillation for the ring oscillator is compared to a reference value. A data value stored within the selected element is determined accordingly. Stored data values remain essentially unaltered when accessed and read by way of the ring oscillator. Memory arrays having memristor or other storage elements can be used according to the present teachings.
摘要翻译：提供了与数据存储元件一起使用的方法和装置。环形振荡器耦合到阵列内的所选择的元件，使得定义反馈环路。将环形振荡器的振荡周期与参考值进行比较。相应地确定存储在所选元素内的数据值。当通过环形振荡器访问和读取时，存储的数据值基本上保持不变。根据本教导，可以使用具有忆阻器或其它存储元件的存储器阵列。

3. 发明授权

US06552925B1 Method of reading a four-transistor memory cell array 失效
标题翻译：读取四晶体管存储单元阵列的方法
公开(公告)号：US06552925B1
公开(公告)日：2003-04-22
申请号：US10062079
申请日：2002-01-31
申请人： Robert J Brooks
发明人： Robert J Brooks
IPC分类号： G11C1100
CPC分类号： G11C11/412 , G11C11/418
摘要： A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
摘要翻译：保持数字状态的一对交叉耦合的反相器由供电功能供电，也可用作行选择和列位线。通过操纵这些行供应线或列供应线来读取和写入单个单元格，单元格行或单元格列的数字状态的方法。读取和写入可以以行或列的形式执行。一种用于读取和逻辑OR或使整个行或列的单元格的方法。一种用于以行或列为基础查询以用作内容可寻址存储器（CAM）的方法。

4. 发明授权

US06832335B2 Transparent software emulation as an alternative to hardware bus lock 有权
标题翻译：透明软件仿真作为硬件总线锁的替代
公开(公告)号：US06832335B2
公开(公告)日：2004-12-14
申请号：US10430395
申请日：2003-05-07
申请人： Robert J Brooks
发明人： Robert J Brooks
IPC分类号： G06F1100
CPC分类号： G06F9/52 , G06F9/45558 , G06F12/10 , G06F2009/45579 , G06F2009/45583
摘要： A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.
摘要翻译：用于在多架构计算机系统中模拟硬件总线锁定的方法和装置包括获取为总线锁定保留的信号量的故障处理程序和限制对页表的访问的信号量。故障处理程序包括一个仿真模块，用于设置模式位以防止总线锁定，并允许重新执行引起硬件总线锁定请求的指令。使用这种方法，故障处理器通过限制对最少量的计算机系统资源的访问来确保对计算机系统的操作的最小的中断。

5. 发明授权

US06587964B1 Transparent software emulation as an alternative to hardware bus lock 失效
公开(公告)号：US06587964B1
公开(公告)日：2003-07-01
申请号：US09504023
申请日：2000-02-18
申请人： Robert J Brooks
发明人： Robert J Brooks
IPC分类号： G06F1100
CPC分类号： G06F9/52 , G06F9/45558 , G06F12/10 , G06F2009/45579 , G06F2009/45583
摘要： A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits access to a page table. The fault handler includes an emulation module that sets a mode bit to prevent the bus lock and allows re-execution of the instruction that caused a request for a hardware bus lock. Using this method, the fault handler ensures a minimum disruption to operation of the computer system by restricting access to the least amount of computer system resources.

6. 发明授权

US06584002B1 Method of querying a four-transistor memory array as a content addressable memory by rows or columns 失效
标题翻译：通过行或列查询四晶体管存储器阵列作为内容可寻址存储器的方法
公开(公告)号：US06584002B1
公开(公告)日：2003-06-24
申请号：US10062053
申请日：2002-01-31
申请人： Robert J Brooks , Alexander J Neudeck
发明人： Robert J Brooks , Alexander J Neudeck
IPC分类号： G11C1504
CPC分类号： G11C15/04
摘要： A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
摘要翻译：保持数字状态的一对交叉耦合的反相器由供电功能供电，也可用作行选择和列位线。通过操纵这些行供应线或列供应线来读取和写入单个单元格，单元格行或单元格列的数字状态的方法。读取和写入可以以行或列的形式执行。一种用于读取和逻辑OR或使整个行或列的单元格的方法。用于以行或列为基础查询以用作内容可寻址存储器（CAM）的方法。

7. 发明授权

US06621728B2 Method of writing a four-transistor memory cell array 失效
标题翻译：写入四晶体管存储单元阵列的方法
公开(公告)号：US06621728B2
公开(公告)日：2003-09-16
申请号：US10061925
申请日：2002-01-31
申请人： Robert J Brooks
发明人： Robert J Brooks
IPC分类号： G11C1100
CPC分类号： G11C11/419 , G11C15/00
摘要： A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
摘要翻译：保持数字状态的一对交叉耦合的反相器由供电功能供电，也可用作行选择和列位线。通过操纵这些行供应线或列供应线来读取和写入单个单元格，单元格行或单元格列的数字状态的方法。读取和写入可以以行或列的形式执行。一种用于读取和逻辑OR或使整个行或列的单元格的方法。用于以行或列为基础查询以用作内容可寻址存储器（CAM）的方法。

8. 发明授权

US06552924B1 Method of reading and logically OR'ing or AND'ing a four-transistor memory cell array by rows or columns 失效
标题翻译：通过行或列读取和逻辑或运算或并入四晶体管存储单元阵列的方法
公开(公告)号：US06552924B1
公开(公告)日：2003-04-22
申请号：US10061876
申请日：2002-01-31
申请人： Robert J Brooks , Alexander J Neudeck
发明人： Robert J Brooks , Alexander J Neudeck
IPC分类号： G11C1100
CPC分类号： G11C11/418 , G11C11/412
摘要： A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
摘要翻译：保持数字状态的一对交叉耦合的反相器由供电功能供电，也可用作行选择和列位线。通过操纵这些行供应线或列供应线来读取和写入单个单元格，单元格行或单元格列的数字状态的方法。读取和写入可以以行或列的形式执行。一种用于读取和逻辑OR或使整个行或列的单元格的方法。用于以行或列为基础查询以用作内容可寻址存储器（CAM）的方法。

9. 发明授权

US09594563B2 CPU archtecture with highly flexible allocation of execution resources to threads 有权
标题翻译： CPU架构具有高度灵活的分配执行资源到线程
公开(公告)号：US09594563B2
公开(公告)日：2017-03-14
申请号：US14144958
申请日：2013-12-31
申请人： Robert J Brooks
发明人： Robert J Brooks
IPC分类号： G06F9/00 , G06F9/32 , G06F9/38 , G06F9/48 , G06F15/80
CPC分类号： G06F9/321 , G06F9/3834 , G06F9/3851 , G06F9/3857 , G06F9/48 , G06F15/8023
摘要： A CPU architecture is proposed which flexibly allocates chip resources among threads. Execution units (microcores) are arranged in a ring. Instruction fetch units (front-ends) deposit instructions sequentially into storage elements within the microcores. Multiple front-ends can each feed segments of the ring; each such segment is a “smart queue”. If, due to a sustained higher execution rate, a thread catches up to the next thread ahead of it, the slower thread steps aside and lets the faster thread play through. Other circumstances may lead to a thread consuming more than its usual share of resources, possibly even all of the microcores, for a time. The architecture has no instruction set dependencies; it is applicable to existing instruction set architectures and will speed up execution of them significantly as compared to conventional architectures.
摘要翻译：提出了一种在线程之间灵活分配芯片资源的CPU架构。执行单位（微点）排列成环。指令提取单元（前端）将指令顺序存入微量库内的存储单元中。多个前端可以各自进给环的段; 每个这样的段是“智能队列”。如果由于持续更高的执行率，一个线程可以追溯到之前的下一个线程，较慢的线程将放在一边，并让更快的线程播放。其他情况可能会导致线程消耗超过其通常的资源份额，甚至可能甚至所有的微博。该架构没有指令集依赖性; 它适用于现有的指令集架构，与传统架构相比，可以显着加快执行速度。

10. 发明授权

US07721133B2 Systems and methods of synchronizing reference frequencies 有权
标题翻译：同步参考频率的系统和方法
公开(公告)号：US07721133B2
公开(公告)日：2010-05-18
申请号：US11412384
申请日：2006-04-27
申请人： Robert J Brooks , Robert J. Blakely , Karl J. Bois
发明人： Robert J Brooks , Robert J. Blakely , Karl J. Bois
IPC分类号： G06F1/12 , H03L7/00
CPC分类号： G06F1/10 , G06F1/12 , G06F11/1604
摘要： System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.
摘要翻译：公开了同步参考频率的系统和方法。在示例性实现中，方法可以包括为多个操作组件中的每一个提供单独的参考频率。该方法还可以包括以模块化的容错电路拓扑将彼此分开的参考频率相互连接。该方法还可以包括使单独的参考频率同步，使得每个操作分量以相同的频率工作。

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