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41. 发明授权

US06225661B1 MOS transistor with stepped gate insulator 有权
标题翻译：带阶梯式栅极绝缘体的MOS晶体管
公开(公告)号：US06225661B1
公开(公告)日：2001-05-01
申请号：US09145786
申请日：1998-09-02
申请人： Judy Xilin An , Bin Yu , Ming-Ren Lin
发明人： Judy Xilin An , Bin Yu , Ming-Ren Lin
IPC分类号： H01L27088
CPC分类号： H01L21/28194 , H01L29/42368 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L2924/0002 , Y10S257/90 , Y10S438/981 , H01L2924/00
摘要： A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.
摘要翻译：在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘。然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。去除间隔物，并用栅电极材料重新填充栅极空隙。

42. 发明授权

US6107667A MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions 有权
标题翻译：具有低k隔离器的MOS晶体管，以抑制栅极和源极/漏极延伸之间的电容耦合
公开(公告)号：US6107667A
公开(公告)日：2000-08-22
申请号：US151146
申请日：1998-09-10
申请人： Judy Xilin An , Bin Yu , Yowjuang W. Liu
发明人： Judy Xilin An , Bin Yu , Yowjuang W. Liu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/76 , H01L27/088 , H01L27/095 , H01L29/94 , H01L31/062
CPC分类号： H01L21/28194 , H01L21/28123 , H01L29/4983 , H01L29/51 , H01L29/66545 , H01L29/6659 , Y10S257/90
摘要： A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.
摘要翻译：制造ULSI MOSFET的方法包括在硅衬底上的场氧化物层中建立空隙并用栅电极填充空隙的中心。高k栅极绝缘体夹在栅电极和衬底之间。围绕空隙，形成低k栅极间隔物，栅极间隔物直接设置在MOSFET的源极和漏极延伸部分的上方。

43. 发明申请

US20090076750A1 INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM 有权
标题翻译：集成电路测试仪信息处理系统
公开(公告)号：US20090076750A1
公开(公告)日：2009-03-19
申请号：US11857272
申请日：2007-09-18
申请人： Sushant S. Suryagandh , Judy Xilin An
发明人： Sushant S. Suryagandh , Judy Xilin An
IPC分类号： G01R19/00
CPC分类号： G01R31/2884 , G01R31/3025 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A method for operating an integrated circuit tester information processing system includes measuring current information from test structures for an integrated circuit having dual stress liners; selecting currents from the current information or stored current information; deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and correlating the stress contribution with the integrated circuit.
摘要翻译：一种用于操作集成电路测试器信息处理系统的方法，包括：测量具有双应力衬垫的集成电路的测试结构的电流信息; 从当前信息或存储的当前信息中选择电流; 基于所述集成电路中的电路元件的有源区域，产生用于应力贡献的电流的比例因子; 并将应力贡献与集成电路相关联。

44. 发明授权

US06407428B1 Field effect transistor with a buried and confined metal plate to control short channel effects 失效
标题翻译：场效应晶体管具有埋置和限制的金属板，以控制短沟道效应
公开(公告)号：US06407428B1
公开(公告)日：2002-06-18
申请号：US09881978
申请日：2001-06-15
申请人： Srinath Krishnan , Judy Xilin An
发明人： Srinath Krishnan , Judy Xilin An
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L21/26506 , H01L21/2658 , H01L29/105 , H01L29/66772 , H01L29/78621
摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region of the FET includes a buried and confined metal plate for controlling short channel effects without significantly increasing junction capacitance.
摘要翻译：在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。 FET的沟道区域包括用于控制短沟道效应的掩埋和限制金属板，而不显着增加结电容。

45. 发明申请

US20090099829A1 INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM FOR NONLINEAR MOBILITY MODEL FOR STRAINED DEVICE 有权
标题翻译：用于应变器件的非线性移动模型的集成电路测试仪信息处理系统
公开(公告)号：US20090099829A1
公开(公告)日：2009-04-16
申请号：US11872509
申请日：2007-10-15
申请人： Rasit Onur Topaloglu , Judy Xilin An
发明人： Rasit Onur Topaloglu , Judy Xilin An
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/3004
摘要： A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve.
摘要翻译：一种用于操作集成电路测试器信息处理系统的方法，包括：测量具有应力衬垫的集成电路的测试结构的电流信息; 通过基于具有第一范围的第一移动性乘数的当前信息进行模拟来形成传递曲线; 通过对转移曲线应用反向传递函数形成逆转移曲线; 从反曲线形成具有第二移动性乘数的应力曲线; 并根据当前信息和基于应力曲线的模拟曲线，通过将测量曲线和模拟曲线与测量曲线进行比较来验证第二移动乘数。

46. 发明授权

US07630850B2 Integrated circuit tester information processing system for nonlinear mobility model for strained device 有权
标题翻译：用于应变器件非线性迁移模型的集成电路测试仪信息处理系统
公开(公告)号：US07630850B2
公开(公告)日：2009-12-08
申请号：US11872509
申请日：2007-10-15
申请人： Rasit Onur Topaloglu , Judy Xilin An
发明人： Rasit Onur Topaloglu , Judy Xilin An
IPC分类号： G01P21/00 , G01R19/00
CPC分类号： G01R31/318357 , G01R31/3004
摘要： A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve.
摘要翻译：一种用于操作集成电路测试器信息处理系统的方法，包括：测量具有应力衬垫的集成电路的测试结构的电流信息; 通过基于具有第一范围的第一移动性乘数的当前信息进行模拟来形成传递曲线; 通过对转移曲线应用反向传递函数形成逆转移曲线; 从反曲线形成具有第二移动性乘数的应力曲线; 并根据当前信息和基于应力曲线的模拟曲线，通过将测量曲线和模拟曲线与测量曲线进行比较来验证第二移动乘数。

47. 发明授权

US07610160B2 Integrated circuit tester information processing system 有权
标题翻译：集成电路测试仪信息处理系统
公开(公告)号：US07610160B2
公开(公告)日：2009-10-27
申请号：US11857272
申请日：2007-09-18
申请人： Sushant S. Suryagandh , Judy Xilin An
发明人： Sushant S. Suryagandh , Judy Xilin An
IPC分类号： G06F19/00
CPC分类号： G01R31/2884 , G01R31/3025 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A method for operating an integrated circuit tester information processing system includes measuring current information from test structures for an integrated circuit having dual stress liners; selecting currents from the current information or stored current information; deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and correlating the stress contribution with the integrated circuit.
摘要翻译：一种用于操作集成电路测试器信息处理系统的方法，包括：测量具有双应力衬垫的集成电路的测试结构的电流信息; 从当前信息或存储的当前信息中选择电流; 基于所述集成电路中的电路元件的有源区域，产生用于应力贡献的电流的比例因子; 并将应力贡献与集成电路相关联。

48. 发明授权

US06509613B1 Self-aligned floating body control for SOI device through leakage enhanced buried oxide 有权
标题翻译：用于SOI器件的自对准浮体控制通过泄漏增强掩埋氧化物
公开(公告)号：US06509613B1
公开(公告)日：2003-01-21
申请号：US09849494
申请日：2001-05-04
申请人： William George En , Srinath Krishnan , Judy Xilin An
发明人： William George En , Srinath Krishnan , Judy Xilin An
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78612
摘要： A semiconductor-on-insulator (SOI) device formed on an SOI structure with a buried oxide (BOX) layer disposed therein and an active region disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The SOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions. The SOI device includes a leakage enhanced region within the BOX layer defined by the gate.
摘要翻译：在SOI结构上形成有埋置氧化物（BOX）层的绝缘体上半导体器件（SOI）器件，以及设置在BOX层上的有源区域，其中有源区域由隔离沟槽和BOX层限定。 SOI器件包括形成在一个有源区上的栅极。栅极限定插入在一个有源区域内形成的源极和漏极之间的沟道。 SOI器件包括由栅极限定的BOX层内的泄漏增强区域。

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