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41. 发明授权

US06535288B1 Machine readable code to trigger data collection 有权
标题翻译：触发数据采集的机器可读代码
公开(公告)号：US06535288B1
公开(公告)日：2003-03-18
申请号：US09902351
申请日：2001-07-10
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
IPC分类号： G01N2189
CPC分类号： H01L21/67253 , C23C14/547 , C23C16/52 , G01N21/47 , G01N21/9501 , H01L22/26
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate comprising an optical indicia and a periodic analysis structure in a periodic manner. The optical indicia is spatially associated with the periodic analysis structure and is utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译：本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。本发明涉及使用散射法来通过以周期性方式分析包括光学标记和周期性分析结构的移动衬底上的薄膜来控制薄膜形成过程。光学标记在空间上与周期性分析结构相关联，并且与信号系统结合使用以确定移动的衬底的位置，由此可以执行移动衬底上相应位置的可重复分析。散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。

42. 发明授权

US06339955B1 Thickness measurement using AFM for next generation lithography 失效
标题翻译：厚度测量采用AFM进行下一代光刻
公开(公告)号：US06339955B1
公开(公告)日：2002-01-22
申请号：US09540251
申请日：2000-03-31
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G01B528
CPC分类号： G01B21/18 , G01B7/066 , G01B21/08 , G01Q30/04 , G01Q80/00 , H01L22/12 , Y10S977/852
摘要： The present invention relates to a method of determining a film thickness and comprises identifying a depth associated with a defect in an underlying material and forming the film over the underlying material. The method further comprises identifying a depth associated with the defect in the film and then using the identified depths to determine the film thickness. The present invention also relates to a system for determining a film thickness and comprises a defect inspection tool operable to identify a location of one or more defects in an underlying material and a topology measurement tool operable to measure a change in topology of a surface. The system also comprises a controller operably coupled to the defect inspection tool and the topology measurement tool. The controller is adapted to receive location information from the defect inspection tool relating to the one or more defects and use the location information to generate and transmit one or more control signals to the topology measurement tool to evaluate a topology of an underlying material and a film at the location corresponding to the one or more defect to thereby generate topology information. Lastly, the controller is adapted to receive the topology information form the topology measurement tool and determine a film thickness using the topology information.
摘要翻译：本发明涉及一种确定膜厚度的方法，包括确定与下层材料中的缺陷有关的深度并在下面的材料上形成薄膜。该方法还包括识别与薄膜中的缺陷相关联的深度，然后使用所识别的深度来确定膜厚度。本发明还涉及一种用于确定膜厚度的系统，并且包括可操作以识别下层材料中的一个或多个缺陷的位置的缺陷检查工具和可操作以测量表面拓扑变化的拓扑测量工具。该系统还包括可操作地耦合到缺陷检查工具和拓扑测量工具的控制器。所述控制器适于接收来自所述缺陷检查工具的与所述一个或多个缺陷有关的位置信息，并使用所述位置信息来生成并发送一个或多个控制信号到所述拓扑测量工具以评估下面的材料和电影的拓扑在与一个或多个缺陷相对应的位置处，从而生成拓扑信息。最后，控制器适于从拓扑测量工具接收拓扑信息，并使用拓扑信息确定膜厚度。

43. 发明授权

US08028531B2 Mitigating heat in an integrated circuit 有权
标题翻译：减轻集成电路中的热量
公开(公告)号：US08028531B2
公开(公告)日：2011-10-04
申请号：US12537135
申请日：2009-08-06
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： F25B21/02
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
摘要翻译：本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

44. 发明申请

US20090288425A1 HEAT REGULATING DEVICE FOR AN INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路的热调节装置
公开(公告)号：US20090288425A1
公开(公告)日：2009-11-26
申请号：US12537135
申请日：2009-08-06
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： F25B21/02 , G05D23/00
CPC分类号： H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathway for inducing heat into and/or dissipating heat away from the integrated circuit, thus creating a more uniform temperature gradient across the semiconductor body.
摘要翻译：本发明提供一种通过采用具有热结构网工作组件的热调节装置来调节和监测集成电路的散热的系统和方法。每个热结构可以用作导热通道，用于将热量从集成电路引入和/或散热，从而在半导体主体上产生更均匀的温度梯度。

45. 发明授权

US06924157B1 Real time particle monitor inside of plasma chamber during resist strip processing 失效
标题翻译：抗蚀带处理过程中等离子体室内实时粒子监测
公开(公告)号：US06924157B1
公开(公告)日：2005-08-02
申请号：US10277003
申请日：2002-10-21
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： H01L21/00
CPC分类号： H01L21/67288 , H01J2237/0225 , H01J2237/3342
摘要： One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.
摘要翻译：本发明的一个方面涉及一种用于在抗蚀剂剥离过程中控制缺陷形成的系统和方法。该系统包括反应室，其包括覆盖半导体结构的图案化抗蚀剂层，其中抗蚀剂层暴露于流入室中的等离子体材料，以便于从结构去除抗蚀剂层;连接的等离子体抗蚀剂颗粒监测系统并且被编程为在抗蚀剂剥离过程期间确定反应室中的颗粒计数，以及耦合到室和反应控制器的反应控制器，反应控制器被编程为从监测系统接收颗粒数据以促进确定室中的计数颗粒是否在可容忍的极限内。该方法包括继续将结构和室暴露于等离子体，直到获得可接受的颗粒数。

46. 发明授权

US06818360B1 Quartz mask crack monitor system for reticle by acoustic and/or laser scatterometry 失效
标题翻译：用于通过声学和/或激光散射测量的石英掩模裂纹监测系统
公开(公告)号：US06818360B1
公开(公告)日：2004-11-16
申请号：US10261571
申请日：2002-09-30
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： G03F900
CPC分类号： G03F1/84 , G01N21/47 , G01N21/9501 , G01N21/956 , G03F1/26
摘要： A system that monitors and controls a phase shift mask fabrication process is disclosed. Acoustic beams and/or beams of light are selectively directed at portions of the mask to scan the mask as it matriculates through the fabrication process. Portions of the beams that pass through and/or are reflected from the mask are collected and examined, such as in accordance with scatterometry based techniques, to determine, for example, whether cracks or other defects are forming on or within the mask, and/or whether features, such as apertures, are being formed as desired. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Controlling the mask fabrication process facilitates improved mask fabrication and resulting chip quality as compared to conventional systems.
摘要翻译：公开了一种监测和控制相移掩模制造工艺的系统。声波束和/或光束被选择性地定向在掩模的部分，以在掩模通过制造过程进入时扫描掩模。通过和/或从掩模反射的光束的部分被收集和检查，例如根据基于散射法的技术，以确定例如是否在掩模上或面罩内形成裂纹或其它缺陷，和/ 或者是否根据需要形成诸如孔的特征。可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。与常规系统相比，控制掩模制造工艺有助于改进掩模制造和产生的芯片质量。

47. 发明授权

US06784446B1 Reticle defect printability verification by resist latent image comparison 有权
标题翻译：光栅缺陷可印刷性验证通过抗蚀剂潜像比较
公开(公告)号：US06784446B1
公开(公告)日：2004-08-31
申请号：US10230714
申请日：2002-08-29
申请人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
发明人： Khoi A. Phan , Bhanwar Singh , Bharath Rangarajan
IPC分类号： G01N2186
CPC分类号： G01N21/95692
摘要： One aspect of the present invention relates to a system and method for detecting defects on a reticle by inspecting latent images printed on a resist wafer by the reticle. The system includes a wafer having a printed photoresist layer formed thereon, a latent image inspection system connected to the wafer exposure system for examining the printed photoresist layer in order to determine whether a reticle employed to print the photoresist layer is defective, and a processor for receiving data from the inspection system in order to verify the presence of defects on the reticle. The method involves printing a first latent image, a second latent image, and a third latent image on a resist wafer using a reticle, and comparing the three latent images to one another to determine whether the reticle is defective. Comparison of the latent images may be facilitated by employing an optical system programmed to perform such comparisons.
摘要翻译：本发明的一个方面涉及通过检查通过掩模版印刷在抗蚀剂晶片上的潜像来检测掩模版上的缺陷的系统和方法。该系统包括其上形成有印刷的光致抗蚀剂层的晶片，连接到晶片曝光系统以检查印刷的光致抗蚀剂层以便确定用于印刷光致抗蚀剂层的掩模版是否有缺陷的潜像检查系统，以及用于从检查系统接收数据，以验证掩模版上是否存在缺陷。该方法包括使用掩模版在抗蚀剂晶片上印刷第一潜像，第二潜像和第三潜像，并将三个潜像彼此进行比较，以确定掩模版是否有缺陷。可以通过使用被编程为执行这种比较的光学系统来促进潜像的比较。

48. 发明授权

US06559457B1 System and method for facilitating detection of defects on a wafer 失效
标题翻译：便于检测晶片缺陷的系统和方法
公开(公告)号：US06559457B1
公开(公告)日：2003-05-06
申请号：US09534410
申请日：2000-03-23
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01J3720
CPC分类号： H01L21/67288 , G01N21/9501 , H01J37/3045 , H01J2237/20292 , H01J2237/2817
摘要： The present invention relates to detecting defects on a wafer. A wafer stage includes markings which are used to form a reference coordinate system. The wafer is positioned on the wafer stage and the wafer is scanned to detect a defect on the wafer. The position of the detected defect is mapped relative to the reference coordinate system of the stage. The location of a reference point on the wafer also is determined in the reference coordinate system. The position of the defect is determined relative to the reference point on the wafer so as to facilitate repeatedly locating the defect on the wafer as the wafer is loaded and reloaded into inspection and processing tools.
摘要翻译：本发明涉及检测晶片上的缺陷。晶片台包括用于形成参考坐标系的标记。将晶片定位在晶片台上，并扫描晶片以检测晶片上的缺陷。检测到的缺陷的位置相对于舞台的参考坐标系映射。参考点在晶片上的位置也在参考坐标系中确定。缺陷的位置相对于晶片上的参考点确定，以便当晶片被装载并重新加载到检查和处理工具中时便于将缺陷重新定位在晶片上。

49. 发明授权

US06291135B1 Ionization technique to reduce defects on next generation lithography mask during exposure 有权
标题翻译：电离技术可减少曝光期间下一代光刻掩模的缺陷
公开(公告)号：US06291135B1
公开(公告)日：2001-09-18
申请号：US09494592
申请日：2000-01-31
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G03F738
CPC分类号： G03F7/168 , Y10S438/906 , Y10S438/944 , Y10S438/949
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving contacting the semiconductor structure including the resist with a plasma comprising at least one inert gas selected from the group consisting of nitrogen, helium, neon, argon, krypton and xenon; exposing the semiconductor structure including the resist to actinic radiation having a wavelength of about 160 nm or less through a lithography mask; and developing the resist with a developer.
摘要翻译：在一个实施方案中，本发明涉及一种处理包括其上的抗蚀剂的半导体结构的方法，包括使包含抗蚀剂的半导体结构与包含至少一种选自氮，氦，氖，氩，氪和氙; 通过光刻掩模将包括抗蚀剂的半导体结构暴露于具有约160nm或更小波长的光化辐射; 并用开发商开发抗蚀剂。

50. 发明授权

US07187796B1 Systems and methods that employ exposure compensation to provide uniform CD control on reticle during fabrication 失效
标题翻译：使用曝光补偿的系统和方法在制造过程中对掩模版提供均匀的CD控制
公开(公告)号：US07187796B1
公开(公告)日：2007-03-06
申请号：US10676613
申请日：2003-10-01
申请人： Khoi A. Phan , Ramkumar Subramanian , Bhanwar Singh
发明人： Khoi A. Phan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： G06K9/00
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/78 , H01J37/3174
摘要： The present invention relates to monitoring and controlling a reticle fabrication process (e.g. employed with an electron beam lithography process). A typical fabrication process involves discrete stages including exposure, post-exposure bake and development. After fabrication is complete, an inspection can be performed on the reticle to determine whether any parameters during fabrication and/or any data points are outside of acceptable tolerances. The data is collected and fed into an algorithm (e.g. data-mining algorithm) utilized to determine which fabrication parameters need to be modified then sends the data to a control system (e.g. advanced process control) to facilitate needed changes to the fabrication parameters.
摘要翻译：本发明涉及监测和控制掩模版制造工艺（例如采用电子束光刻工艺）。典型的制造过程涉及离散阶段，包括曝光，曝光后烘烤和显影。制造完成后，可以对掩模版进行检查，以确定制造期间和/或任何数据点中的任何参数是否超出可接受的公差。收集数据并将其馈送到用于确定哪些制造参数需要被修改的算法（例如数据挖掘算法）中，然后将数据发送到控制系统（例如高级过程控制），以便于对制造参数的所需改变。

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