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41. 发明授权

US07432579B2 Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate 失效
标题翻译：在单个基板上提供具有水平MOSFET和肖特基势垒二极管的半导体器件
公开(公告)号：US07432579B2
公开(公告)日：2008-10-07
申请号：US10959201
申请日：2004-10-07
申请人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
发明人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L27/0727
摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.
摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层，所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一和第二漏区。

42. 发明授权

US07115946B2 MOS transistor having an offset region 有权
标题翻译： MOS晶体管具有偏移区域
公开(公告)号：US07115946B2
公开(公告)日：2006-10-03
申请号：US09956015
申请日：2001-09-20
申请人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
发明人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/0696 , H01L29/0847 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66674 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a semiconductor region of a first conductivity type, a drain region of the first conductivity type, an offset region of the first conductivity type, a body region of the second conductivity type, a source region of the first conductivity type, a gate insulating film and a gate electrode. The drain region is provided in a surface of the semiconductor region and is shaped like a stripe. The offset region is provided in the surface of the semiconductor region and surrounds the drain region. The body region is provided in the surface of the semiconductor region and surrounds the offset region. The source region is provided in a surface of the body region and surrounds the offset region. The gate insulating film is provided on a part of the body region. The gate electrode is provided on the gate insulating film.
摘要翻译：半导体器件包括第一导电类型的半导体区域，第一导电类型的漏极区域，第一导电类型的偏移区域，第二导电类型的体区域，第一导电类型的源极区域，栅极绝缘膜和栅电极。漏极区域设置在半导体区域的表面中并且形状为条状。偏移区域设置在半导体区域的表面中并且围绕漏极区域。身体区域设置在半导体区域的表面中并且包围偏移区域。源区域设置在身体区域的表面中并且围绕偏移区域。栅极绝缘膜设置在身体区域的一部分上。栅电极设置在栅极绝缘膜上。

43. 发明授权

US07061048B2 Power MOSFET device 失效
公开(公告)号：US07061048B2
公开(公告)日：2006-06-13
申请号：US10790137
申请日：2004-03-02
申请人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
发明人： Yusuke Kawaguchi , Norio Yasuhara , Syotaro Ono , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L27/96
CPC分类号： H01L21/26513 , H01L29/04 , H01L29/0653 , H01L29/0847 , H01L29/0878 , H01L29/1045 , H01L29/1095 , H01L29/41 , H01L29/4175 , H01L29/42372 , H01L29/42376 , H01L29/66659 , H01L29/66712 , H01L29/7802 , H01L29/7835
摘要： A power MOSFET device comprising a low resistance substrate of the first conductivity type, a high resistance epitaxial layer of the first conductivity type formed on the low resistance substrate, a base layer of the second conductivity type formed in a surface region of the high resistance epitaxial layer, a source region of the first conductivity type formed in a surface region of the base layer, a gate insulating film formed on the surface of the base layer so as to contact the source region, a gate electrode formed on the gate insulating film, and an LDD layer of the first conductivity type formed on the surface of the high resistance epitaxial layer oppositely relative to the source region and the gate electrode, wherein the LDD layer and the low resistance substrate are connected to each other by the high resistance epitaxial layer.

44. 发明申请

US20060055432A1 Semiconductor module 失效
公开(公告)号：US20060055432A1
公开(公告)日：2006-03-16
申请号：US11214730
申请日：2005-08-31
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H03D13/00
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

45. 发明申请

US20050287744A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050287744A1
公开(公告)日：2005-12-29
申请号：US11157908
申请日：2005-06-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/336 , H01L29/06 , H01L29/76 , H01L29/78 , H01L29/872 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/7806 , H01L29/872
摘要： A semiconductor device has a plurality of pillars formed by filling a poly-silicon via an insulating layer in a plurality of trenches arranged substantially in parallel at certain intervals, n+-semiconductor regions and p+-semiconductor regions which are formed between partial pillars among the plurality of pillars and alternately formed along a direction where the pillars extend, n−-semiconductor regions arranged between the other partial neighboring pillars among the plurality of pillars and a first metal layer which makes a schottky contact on an upper face of the n−-semiconductor regions.
摘要翻译：半导体器件具有通过多个沟槽中的绝缘层填充多晶硅形成的多个柱，所述多个沟槽基本上以一定间隔平行设置，n + + - 半导体区域和p + 在多个柱之间的部分柱之间形成并且沿着柱延伸的方向交替形成的半导体区域，其间布置在其中的相邻部分相邻柱之间的半导体区域多个柱状物以及在第n个半导体区域的上表面上形成肖特基接触的第一金属层。

46. 发明授权

US06914294B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06914294B2
公开(公告)日：2005-07-05
申请号：US10438069
申请日：2003-05-15
申请人： Kazutoshi Nakamura , Tomoko Matsudai , Yusuke Kawaguchi , Akio Nakagawa
发明人： Kazutoshi Nakamura , Tomoko Matsudai , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/78 , H01L31/113
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1083 , H01L29/7801
摘要： A semiconductor device comprises a semiconductor substrate having a main surface; a semiconductor layer of a first conduction type provided on the main surface of said semiconductor substrate; a first buried layer of the first conduction type provided between said semiconductor layer and said semiconductor substrate; a first connection region of the first conduction type provided around said first buried layer, said first connection region extending from the surface of said semiconductor layer to said first buried layer; a switching element provided in the surface region of said semiconductor layer on said first buried layer; and a low breakdown-voltage element provided in a surface region of said semiconductor layer, said low breakdown-voltage element being closer to said first connection region than said switching element and having lower breakdown voltage than that of said switching element.
摘要翻译：半导体器件包括具有主表面的半导体衬底; 设置在所述半导体衬底的主表面上的第一导电类型的半导体层; 设置在所述半导体层和所述半导体衬底之间的第一导电类型的第一掩埋层; 所述第一导电类型的第一连接区域设置在所述第一掩埋层周围，所述第一连接区域从所述半导体层的表面延伸到所述第一掩埋层; 设置在所述第一掩埋层的所述半导体层的表面区域中的开关元件; 以及设置在所述半导体层的表面区域中的低击穿电压元件，所述低击穿电压元件比所述开关元件更靠近所述第一连接区域，并且具有比所述开关元件的击穿电压低的击穿电压。

47. 发明申请

US20050056890A1 Offset-gate-type semiconductor device 失效
标题翻译：偏移栅型半导体器件
公开(公告)号：US20050056890A1
公开(公告)日：2005-03-17
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.
摘要翻译：半导体器件包括具有第一导电类型的第一半导体区域，形成在第一半导体区域上并且具有第一导电类型的第二半导体区域，形成在第二半导体区域的表面中并具有第二导电类型的第三半导体区域形成在第二半导体区域的表面上并具有第二导电类型的第四半导体区域以及形成在第二和第四半导体区域上的栅极结构。半导体器件还包括布置在从第四半导体区域的表面延伸到第一半导体区域的沟槽中的导电构件，沟槽具有与栅极结构的侧壁表面齐平的一个侧壁表面。

48. 发明授权

US06864533B2 MOS field effect transistor with reduced on-resistance 有权
公开(公告)号：US06864533B2
公开(公告)日：2005-03-08
申请号：US09949646
申请日：2001-09-12
申请人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
发明人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/41766 , H01L29/7801 , H01L29/7818 , H01L29/7824 , H01L29/7833 , H01L29/7835
摘要： A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

49. 发明申请

US20050029586A1 Semiconductor device having trench gate structure and manufacturing method thereof 有权
标题翻译：具有沟槽栅极结构的半导体器件及其制造方法
公开(公告)号：US20050029586A1
公开(公告)日：2005-02-10
申请号：US10682111
申请日：2003-10-10
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/336 , H01L29/08 , H01L29/267 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/267 , H01L29/42368 , H01L29/4933
摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.
摘要翻译：垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低比第一个高峰。基于第一峰确定阈值电压，并且基于第二峰确定剂量。

50. 发明授权

US06838730B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06838730B1
公开(公告)日：2005-01-04
申请号：US10781688
申请日：2004-02-20
申请人： Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi , Akio Nakagawa
发明人： Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0847 , H01L29/4236 , H01L29/4238
摘要： A semiconductor device comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed in an upper surface of the first semiconductor layer, resistance of the second semiconductor layer being higher than that of the first semiconductor layer, a base layer of a second conductivity type formed on the second semiconductor layer, gate electrodes deposited in a plurality of first trenches, a gate insulation film being disposed between inner walls and the gate electrodes, each of the first trenches having a band-shaped planar pattern and extending from top of the base layer down to the upper surface of the second semiconductor layer, bridge electrodes filling a plurality of second trenches and surrounded by an insulation film deposited over walls of the trenches, the second trenches extending from the top of the base layer down to the upper surface of the second semiconductor layer and connecting adjacent ones of the first trenches in communication with one another so that each of the bridge electrodes electrically connects adjacent ones of the gate electrodes, an impurity diffused region of the second conductivity type formed in the second semiconductor layer adapted to surround the second trenches existing in the second semiconductor layer, a source region of the first conductivity type formed in a surface area of the base layer alongside extensions of the gate electrodes, a source electrode formed on the surface of the source region, and a drain electrode formed on a back surface of the first semiconductor layer.
摘要翻译：半导体器件包括第一导电类型的第一半导体层，形成在第一半导体层的上表面中的第一导电类型的第二半导体层，第二半导体层的电阻高于第一半导体层的电阻，形成在第二半导体层上的第二导电类型的基极层，沉积在多个第一沟槽中的栅电极，栅极绝缘膜设置在内壁和栅电极之间，每个第一沟槽具有带状平面图案并从基底层的顶部向下延伸到第二半导体层的上表面，桥接电极填充多个第二沟槽并由沉积在沟槽的壁上的绝缘膜围绕，第二沟槽从第二沟槽的顶部延伸基底层向下延伸到第二半导体层的上表面并且连接相邻的第一熔丝 t沟槽彼此连通，使得每个桥电极电连接相邻的栅极电极，形成在第二半导体层中的适于包围存在于第二半导体层中的第二沟槽的第二导电类型的杂质扩散区域形成在基极层的表面区域的栅极电极的延伸部分上形成的第一导电类型的源极区域，形成在源极区域的表面上的源极电极和形成在第一半导体的背面上的漏极电极层。

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