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    • 44. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE WITH COLUMN TO BE SELECTED BY BIT LINE SELECTION SIGNAL
    • 具有通过位线选择信号选择的列的半导体存储器件
    • US20080031065A1
    • 2008-02-07
    • US11865398
    • 2007-10-01
    • Yasuyuki KAJITANIDaisuke KatoMariko Kaku
    • Yasuyuki KAJITANIDaisuke KatoMariko Kaku
    • G11C7/02
    • G11C11/4087G11C7/08G11C11/4091G11C29/808G11C2207/002
    • A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit line pair and the data line pair in accordance with a bit line selection signal. A control circuit controls the bit line selection signal supplied to the selection circuits. A global bit line selection signal line is connected to the control circuit, and receives the bit line section signal therefrom. Drive circuits, input portions of which are connected to the global bit line selection signal line, drive the bit line selection signal supplied to the global bit line selection signal line and output it, and the drive circuits are arranged within the sense amplifier bank. A local bit line selection signal line supplies the bit line selection signal driven by the drive circuit to the selection circuit.
    • 读出放大器组包含读出放大器电路,数据线对和选择电路。 选择电路根据位线选择信号设置位线对和数据线对之间的连接状态和断开状态之一。 控制电路控制提供给选择电路的位线选择信号。 全局位线选择信号线连接到控制电路,并从其接收位线部分信号。 驱动电路,其输入部分连接到全局位线选择信号线,驱动提供给全局位线选择信号线的位线选择信号并将其输出,驱动电路被布置在读出放大器组内。 局部位线选择信号线将由驱动电路驱动的位线选择信号提供给选择电路。
    • 48. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06856561B2
    • 2005-02-15
    • US10657790
    • 2003-09-08
    • Daisuke KatoMunehiro YoshidaYohji Watanabe
    • Daisuke KatoMunehiro YoshidaYohji Watanabe
    • G11C29/00G11C7/00
    • G11C29/808G11C29/785
    • A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.
    • 半导体存储器件具有单元阵列,每个在单元阵列内定义的第一法向元件作为沿单元阵列的第一方向布置的一组存储单元,每个在单元阵列内被定义为一组存储单元,每个存储单元被布置 在所述单元阵列的第二方向上,每个所述第二普通元件选择与所述第一正常元件中的对应的一个操作关联的存储器单元,用于替换所述单元阵列内的有缺陷的第一正常元件的第一冗余元件和所述第二冗余元件 用于替换电池阵列内的有缺陷的第二正常元件的元件。 在单元阵列第一/第二修复区域内被定义为具有允许由每个第一/第二冗余元件替换的第一/第二正常元素的组。