专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US4780810A Data processor with associative memory storing vector elements for vector conversion 失效
标题翻译：具有相关存储器的数据处理器，用于存储向量转换的向量元素
公开(公告)号：US4780810A
公开(公告)日：1988-10-25
申请号：US737453
申请日：1985-05-24
申请人： Shunichi Torii , Keiji Kojima , Noriyasu Ido
发明人： Shunichi Torii , Keiji Kojima , Noriyasu Ido
IPC分类号： G11C15/04 , G06F15/78 , G06F17/16 , G06F17/30 , G06F15/347 , G06F5/00
CPC分类号： G06F15/8076 , G06F17/30949 , G06F17/30982
摘要： Associative keys and retrieve outputs corresponding thereto are registered to an associative memory in a vector data conversion apparatus. Conversion vector data stored in the main storage and comprising vector elements of the same type of an associative key is sequentially read out for each vector element and is inputted to a comparator, which then compares the vector element with the associative keys beforehand registered to the associative memory so as to determine whether or not a matching condition exists therebetween. When the comparator detects the matching condition, a retrieve output corresponding to the matched associative key is read out from the associative memory and is stored in the main storage. While the conversion vector data is sequentially read out for each vector in this manner, the retrieve output data is sequentially stored in the main storage so as to generate the converted vector data comprising the retrieve output data as vector elements. A user identifier may also be inputted as a compare element together with the associative key, thereby preventing an erroneous data conversion from taking place even when a plurality of users share the vector data conversion apparatus.
摘要翻译：相关键和检索对应的输出被登记到矢量数据转换装置中的关联存储器。存储在主存储器中并且包括相关类型的关联键的向量元素的转换矢量数据被顺序地读出用于每个向量元素，并且被输入到比较器，比较器将比较矢量元素与预先登记到关联关联的关联密钥存储器，以便确定它们之间是否存在匹配条件。当比较器检测到匹配条件时，从关联存储器读出对应于匹配关联密钥的检索输出，并存储在主存储器中。虽然以这种方式顺序地读取每个向量的转换向量数据，但是检索输出数据被顺序地存储在主存储器中，以便生成包括作为向量元素的检索输出数据的转换的向量数据。也可以将用户标识符与关联密钥一起作为比较元素输入，从而即使当多个用户共享向量数据转换装置时也防止错误的数据转换。

42. 发明授权

US4760551A Operation unit for floating point data with variable exponent-part length 失效
标题翻译：具有可变指数部分长度的浮点数据的操作单元
公开(公告)号：US4760551A
公开(公告)日：1988-07-26
申请号：US808476
申请日：1985-12-13
申请人： Goichi Yokomizo , Shunichi Torii , Hozumi Hamada
发明人： Goichi Yokomizo , Shunichi Torii , Hozumi Hamada
IPC分类号： G06F7/00 , G06F7/48 , G06F7/76 , G06F5/00
CPC分类号： G06F7/48 , G06F2207/3816
摘要： An operation unit has a significant digit number judging circuit in which to detect as to whether or not a significant digit number of exponent part variable length data obtained as an arithmetic result becomes smaller than a specified minimum significant digit number, this operation unit manipulating data characterized in that exponent and mantissa parts thereof vary in length according to data values and its data length is fixed. In a first embodiment, there is a circuit for detecting the significant digit number of the resultant data with a variable length exponent part, the data being gained by a step wherein exponent and mantissa data are combined by using the exponent data of the resultant fixed length exponent and mantissa data. A second embodiment involves utilization of a circuit in which to detect as to whether or not the significant digit number is lower than a predetermined significant digit number by directly employing the resultant data with the variable length exponent part which data are procured after completion of the combination.
摘要翻译：操作单元具有有效的数字数判断电路，其中检测作为算术结果获得的指数部分可变长度数据的有效位数是否小于指定的最小有效数字号，该操作单元操作表示的数据因为其指数和尾数部分根据数据值的长度而变化，并且其数据长度是固定的。在第一实施例中，存在用于用可变长度指数部分检测结果数据的有效位数的电路，该数据是通过使用所得到的固定长度的指数数据组合指数和尾数数据的步骤获得的指数和尾数数据。第二实施例涉及利用其中通过直接使用结果数据与可变长度指数部分来检测有效数字数是否低于预定有效数字数字的电路，该可变长度指数部分在组合完成之后获得数据。

43. 发明授权

US4723206A Vector processor 失效
标题翻译：矢量处理器
公开(公告)号：US4723206A
公开(公告)日：1988-02-02
申请号：US737686
申请日：1985-05-24
申请人： Keiji Kojima , Shunichi Torii , Noriyasu Ido
发明人： Keiji Kojima , Shunichi Torii , Noriyasu Ido
IPC分类号： G06F7/04 , G06F15/78 , G06F17/16 , G06F15/347
CPC分类号： G06F15/8053
摘要： A vector to be processed consisting of a plurality of partial vectors each having a variable number of vector elements and a key vector consisting of a fixed number of vector elements are vector-processed while the vector elements of those vectors are sequentially read out. A vector processor has a punctuation detection circuit for detecting a punctuation between the partial vectors in the vector to be processed. The reading of the key vector is restored to the reading of the start vector element in accordance with the detection signal from the punctuation detection circuit.
摘要翻译：对由矢量进行矢量处理的矢量进行矢量处理，该矢量由具有可变数量的矢量元素的多个部分矢量和由固定数量的向量元素构成的关键矢量构成。矢量处理器具有用于检测待处理矢量中的部分矢量之间的标点符号的标点符号检测电路。根据来自标点符号检测电路的检测信号，将键向量的读取恢复为起始向量元素的读取。

44. 发明授权

US4541046A Data processing system including scalar data processor and vector data processor 失效
标题翻译：数据处理系统包括标量数据处理器和矢量数据处理器
公开(公告)号：US4541046A
公开(公告)日：1985-09-10
申请号：US361478
申请日：1982-03-23
申请人： Shigeo Nagashima , Shunichi Torii , Koichiro Omoda , Yasuhiro Inagami
发明人： Shigeo Nagashima , Shunichi Torii , Koichiro Omoda , Yasuhiro Inagami
IPC分类号： G06F9/38 , G06F15/78 , G06F15/31
CPC分类号： G06F9/3887 , G06F15/8061 , G06F9/30036 , G06F9/3879
摘要： A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.
摘要翻译：矢量处理器包括用于存储用于执行期望操作的标量指令链和矢量指令链的主存储器，以及用于分别取出标量指令链和向量指令链的标量处理单元和向量处理单元，对它们进行解码并执行它们标量处理和向量处理以重叠的方式执行。

45. 发明授权

US4525796A Pipelined operation unit for vector data 失效
标题翻译：用于矢量数据的流水线操作单元
公开(公告)号：US4525796A
公开(公告)日：1985-06-25
申请号：US347720
申请日：1982-02-10
申请人： Koichiro Omoda , Yasuhiro Inagami , Shunichi Torii , Shigeo Nagashima
发明人： Koichiro Omoda , Yasuhiro Inagami , Shunichi Torii , Shigeo Nagashima
IPC分类号： G06F17/16 , G06F7/544 , G06F9/38 , G06F15/78 , G06F7/00
CPC分类号： G06F15/8053 , G06F7/5443 , G06F9/3885
摘要： In an operation unit wherein a series of data is sequentially applied, a predetermined operation is performed in synchronism with the input data in a pipelined manner, and the predetermined operation is applied to an input data and the result of the predetermined operation for a preceding input data. There are provided a plurality of partial operation devices which respectively compute a plurality of different partial data of a result data to be obtained as a result of the predetermined operation, and when one of the partial data is obtained, the one partial data is immediately used for the operation for the subsequent input data. Consequently, the operation for the subsequent input data can be started before the operation for the remainder of the partial data of the preceding input data is completed.
摘要翻译：在顺序地应用一系列数据的操作单元中，以流水线方式与输入数据同步地执行预定操作，并且将预定操作应用于输入数据，并将预定操作的结果用于前一个输入数据。提供了多个部分操作装置，其分别计算作为预定操作的结果将要获得的结果数据的多个不同部分数据，并且当获得部分数据之一时，立即使用一个部分数据用于后续输入数据的操作。因此，在完成前一输入数据的部分数据的其余部分的操作之前，可以开始后续输入数据的操作。

46. 发明授权

US4385351A Multiprocessor system with apparatus for propagating cache buffer invalidation signals around a circular loop 失效
标题翻译：多处理器系统，具有围绕圆形循环传播缓存无效信号的装置
公开(公告)号：US4385351A
公开(公告)日：1983-05-24
申请号：US136492
申请日：1980-04-03
申请人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
发明人： Tsuguo Matsuura , Shunichi Torii , Tsuguo Shimizu
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173 , G06F7/02 , G06F11/00 , G06F15/00
CPC分类号： G06F12/0813
摘要： This data processing system includes a main memory which is shared by a plurality of central processor units (CPUs) which are also coupled in cascade in a closed circular path. Each CPU has a cache buffer memory and two sets of transfer registers for receiving and transmitting cancel request signals which identify cache data which is no longer valid. Each CPU's receiving register subsystem includes circuitry for invalidating cache buffer data which has been updated or rewritten in main memory by another CPU in the loop. Each CPU's transmitting register subsystem includes circuitry for inhibiting the transmittal of a cancel request signal if the next CPU in the circle is the same one which originated the particular cache invalidation signal. Circuitry is also provided for propagating a cancel request signal around the loop in opposite directions simultaneously.
摘要翻译：该数据处理系统包括由多个中央处理器单元（CPU）共享的主存储器，这些中央处理器单元也是以闭合的圆形路径级联耦合的。每个CPU具有高速缓存存储器和两组传输寄存器，用于接收和发送识别不再有效的高速缓存数据的取消请求信号。每个CPU的接收寄存器子系统包括用于使循环中的另一个CPU更新或重写在主存储器中的缓存缓冲器数据无效的电路。每个CPU的发送寄存器子系统包括如果圆中的下一个CPU是相同的，发起特定的高速缓存无效信号，则禁止发送取消请求信号的电路。还提供电路用于在相反方向上同时传播环路周围的取消请求信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式