专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5901097A Read bus controlling apparatus for semiconductor storage device 失效
标题翻译：读取半导体存储装置的总线控制装置
公开(公告)号：US5901097A
公开(公告)日：1999-05-04
申请号：US859715
申请日：1997-05-21
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1048 , G11C11/4096
摘要： The invention provides a semiconductor storage device which is comparatively short in read time. A read route is formed from a first read bus pair connected to a plurality of sense amplifiers, to which a bit line pair is inputted, and inputted to a first data amplifier, a second read bus pair connected to the first data amplifier connected to the sense amplifiers, to which the bit line pair is inputted, and also to a precharge circuit and inputted to a second data amplifier, a third read bus outputted from the second data amplifier and inputted to a data output buffer, and a bus extending from the data output buffer to an output terminal. The precharge circuit is connected to the second read buses in the proximity of the first data amplifier connected to the second read buses at a position remote from the connection points between the second data amplifier and the second read buses.
摘要翻译：本发明提供一种读取时间相对较短的半导体存储装置。从连接到多个读出放大器的第一读取总线对形成读取路由，输入位线对，并将其输入到第一数据放大器，连接到连接到第一数据放大器的第一数据放大器的第二读取总线对输入位线对的读出放大器，以及输入到第二数据放大器的预充电电路，从第二数据放大器输出并输入到数据输出缓冲器的第三读总线，以及从第数据输出缓冲区到输出端。在远离第二数据放大器和第二读出总线之间的连接点的位置处，预充电电路连接到第二数据放大器附近的第二数据放大器接近第二读总线。

42. 发明授权

US5867447A Synchronous semiconductor memory having a write execution time dependent upon a cycle time 失效
标题翻译：具有取决于循环时间的写入执行时间的同步半导体存储器
公开(公告)号：US5867447A
公开(公告)日：1999-02-02
申请号：US745821
申请日：1996-11-12
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C11/413 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a synchronous semiconductor memory, there is provided a write pulse generating circuit receiving a pipeline enable signal, a write enable signal and an internal synchronous signal which is generated by delaying an output of an internal synchronous signal generating circuit by a first delay. This write pulse generating circuit includes a second delay, and is configured to generate a write pulse which is put into an inactivate condition for a constant time corresponding to a delay time of the second delay when the internal synchronous signal is brought to a high level, and thereafter, is maintained in an activate condition until the next internal synchronous signal is supplied. Thus, by adjusting the delay amount of the first delay and the delay amount of the second delay, a column selection line is never switched during a period that a write data is being supplied to write bus pairs, so that the write data is accurately written into a sense amplifier. Thus, the write execution time depends upon the cycle time, with the result that the cycle time for the writing can be shortened.
摘要翻译：在同步半导体存储器中，提供了一个写入脉冲发生电路，其接收管线使能信号，写使能信号和内部同步信号，该信号是通过延迟内部同步信号产生电路的输出而产生的。该写入脉冲发生电路包括第二延迟，并且被配置为当内部同步信号达到高电平时，产生与第二延迟的延迟时间对应的恒定时间的失活条件的写入脉冲，然后，保持在激活状态，直到提供下一个内部同步信号。因此，通过调整第一延迟的延迟量和第二延迟的延迟量，在写入数据被提供给写入总线对的时段期间，列选择线不会切换，使得写入数据被准确地写入进入感测放大器。因此，写入执行时间取决于周期时间，结果可以缩短写入的周期时间。

43. 发明授权

US5289061A Output gate for a semiconductor IC 失效
标题翻译：半导体IC的输出门
公开(公告)号：US5289061A
公开(公告)日：1994-02-22
申请号：US937055
申请日：1992-08-26
申请人： Tadahiko Sugibayashi , Yasuji Koshikawa , Ryuji Yamamura
发明人： Tadahiko Sugibayashi , Yasuji Koshikawa , Ryuji Yamamura
IPC分类号： H03K19/0948 , G11C11/407 , G11C11/409 , H03K19/0185 , H03K5/00
CPC分类号： H03K19/018521
摘要： An output gate according to the present invention includes a CMOS gate composed of a P-MOS transistor connected at a source to an external power supply and a first N-MOS transistor connected at a source to ground, and a second N-MOS transistor connected between ground and the first N-MOS transistor by a source-drain path. The second N-MOS transistor is connected at a gate to an external power supply.
摘要翻译：根据本发明的输出门包括由源极连接到外部电源的P-MOS晶体管和连接到源极的第一N-MOS晶体管构成的CMOS栅极和连接到第二N-MOS晶体管的第二N-MOS晶体管通过源极 - 漏极路径在地和第一N-MOS晶体管之间。第二N-MOS晶体管在栅极连接到外部电源。

44. 发明授权

US5287011A Power-on detecting circuit desirable for integrated circuit equipped with internal step-down circuit 失效
标题翻译：上电检测电路适用于配有内部降压电路的集成电路
公开(公告)号：US5287011A
公开(公告)日：1994-02-15
申请号：US912756
申请日：1992-07-13
申请人： Yasuji Koshikawa , Takahiro Hara , Tadahiko Sugibayashi
发明人： Yasuji Koshikawa , Takahiro Hara , Tadahiko Sugibayashi
IPC分类号： G11C11/401 , G11C11/407 , H03K17/14 , H03K17/22 , H03K3/01
CPC分类号： H03K17/22 , H03K17/145
摘要： A power-on detecting circuit produces a power-on signal upon power-on event for initializing internal component circuits, and comprises a timing generating unit for producing a timing signal when a power voltage level reaches a predetermined voltage level, a monitoring unit for producing an enable signal when a step-down power voltage level reaches a constant level, and a signal generating unit for producing the power-on signal in the concurrent presence of the enable signal and the timing signal, thereby guaranteeing the initialization of the internal component circuits.
摘要翻译：上电检测电路在用于初始化内部组件电路的电源接通事件时产生通电信号，并且包括用于在电源电压达到预定电压电平时产生定时信号的定时产生单元，用于产生当降压功率电压电平达到恒定电平时的使能信号，以及用于在同时存在使能信号和定时信号时产生通电信号的信号产生单元，从而保证内部组件电路的初始化。

45. 发明授权

US08015457B2 Redundancy circuit and semiconductor memory device 有权
标题翻译：冗余电路和半导体存储器件
公开(公告)号：US08015457B2
公开(公告)日：2011-09-06
申请号：US12000373
申请日：2007-12-12
申请人： Yasuji Koshikawa , Yousuke Kawamata
发明人： Yasuji Koshikawa , Yousuke Kawamata
IPC分类号： G11C29/44 , G11C29/50
CPC分类号： G11C17/14 , G11C29/02 , G11C29/027 , G11C29/835
摘要： Disclosed is a circuit for deciding whether or not a plural number of redundancy ROM circuits have been programmed in a preset order, with regards to addresses. In at least one of first to n-th redundancy memory circuits, an address to be substituted by a redundant address is recorded and a redundancy selection signal is output when an access address is coincident with the programmed address. It is presupposed that repair addresses are programmed from the first to the n-th redundancy ROM circuits in an ascending order with regards to address. If it is detected under this condition that a redundancy selection signal has been output from the i+1'st redundancy memory circuit while no redundancy selection signal is being output from the i-th redundancy memory circuit, an SR flip-flop is set and the sequence of the substitution decision outputs is decided to be a reversed sequence.
摘要翻译：公开了一种用于判定多个冗余ROM电路是否已经以预设顺序对地址进行编程的电路。在第一至第n冗余存储器电路中的至少一个中，记录要由冗余地址替代的地址，并且当访问地址与编程的地址一致时，输出冗余选择信号。假设修复地址从第一到第n冗余ROM电路以关于地址的升序被编程。如果在该条件下检测到从第i + 1'冗余存储电路输出了冗余选择信号，而没有从第i冗余存储电路输出冗余选择信号，则设置SR触发器，替代决策输出的顺序被确定为逆序列。

46. 发明授权

US07835213B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07835213B2
公开(公告)日：2010-11-16
申请号：US12325026
申请日：2008-11-28
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C5/14
CPC分类号： G11C7/1051 , G11C7/1057 , G11C11/404 , G11C11/407 , H01L21/823462 , H01L27/105 , H01L27/10873 , H01L27/10897
摘要： A semiconductor memory device with low power consumption and improved transfer rate of an input/output buffer at reduced manufacturing cost is provided. Thick-film transistors are used for a memory cell array 33, a row decoder 30, and a sense amplifier 32, surrounded by a bold broken line. Thick-film transistors having a threshold voltage lower than the aforementioned transistors are used for input buffers 11 to 13 and an input/output buffer 26, surrounded by a bold line. Thin-film transistors are used for a clock generator 16, a command decoder 17, a mode register 18, a controller 20, a row address buffer and refresh counter 21, a column address buffer and burst counter 22, a data control circuit 23, a latch circuit 24, a DLL 25, and a column decoder 31.
摘要翻译：提供了一种半导体存储器件，其以降低的制造成本具有低功耗和改善的输入/输出缓冲器的传送速率。厚膜晶体管用于由粗体虚线包围的存储单元阵列33，行解码器30和读出放大器32。具有低于上述晶体管的阈值电压的厚膜晶体管用于由粗线包围的输入缓冲器11至13和输入/输出缓冲器26。薄膜晶体管用于时钟发生器16，命令解码器17，模式寄存器18，控制器20，行地址缓冲器和刷新计数器21，列地址缓冲器和突发计数器22，数据控制电路23，锁存电路24，DLL 25和列解码器31。

47. 发明授权

US07652904B2 Semiconductor memory device having plural memory cell arrays 有权
标题翻译：具有多个存储单元阵列的半导体存储器件
公开(公告)号：US07652904B2
公开(公告)日：2010-01-26
申请号：US11956448
申请日：2007-12-14
申请人： Chiaki Dono , Yasuji Koshikawa , Jun Suzuki
发明人： Chiaki Dono , Yasuji Koshikawa , Jun Suzuki
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/06
摘要： A semiconductor memory device includes first and second bus regions, a third bus region laid out along a center line, a first cell region laid out between a first side and the first bus region, a second cell region laid out between a second side and the second bus region, third and fourth cell regions laid out between the first and second bus regions and laid out toward a third side and a fourth side respectively seen from the third bus region, and a data input/output pad string laid out along the third bus region.
摘要翻译：半导体存储器件包括第一和第二总线区域，沿着中心线布置的第三总线区域，布置在第一侧面与第一总线区域之间的第一单元区域，布置在第二侧面与第二区域之间的第二单元区域，第二总线区域，第三和第四单元区域，布置在第一和第二总线区域之间并且分别朝向从第三总线区域看到的第三侧面和第四侧面布置，以及沿着第三总线区域布置的数据输入/输出焊盘串巴士区。

48. 发明授权

US07417908B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07417908B2
公开(公告)日：2008-08-26
申请号：US10564626
申请日：2004-07-13
申请人： Sumio Ogawa , Yasuji Koshikawa
发明人： Sumio Ogawa , Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

49. 发明授权

US07075852B2 Semiconductor memory device of hierarchy word type and sub word driver circuit 有权
标题翻译：层级字类型和子字驱动电路半导体存储器件
公开(公告)号：US07075852B2
公开(公告)日：2006-07-11
申请号：US10972486
申请日：2004-10-26
申请人： Chiaki Dono , Yasuji Koshikawa
发明人： Chiaki Dono , Yasuji Koshikawa
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C8/08
摘要： In a sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, a first NMOS transistor and a first PMOS transistor are connected in series. A second NMOS transistor is connected with a node between the first PMOS transistor and the first NMOS transistor. The source of the first PMOS transistor is connected with a sub word line inverted signal obtained by inverting the sub word line signal, and the source of the first NMOS transistor is connected with a first negative voltage. A single main word line signal is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and the sub word line signal is connected with a gate of the second NMOS transistor.
摘要翻译：在使用主字线信号和子字线信号的分层字结构的半导体存储器件中的子字驱动器电路中，串联连接第一NMOS晶体管和第一PMOS晶体管。第二NMOS晶体管与第一PMOS晶体管和第一NMOS晶体管之间的节点连接。第一PMOS晶体管的源极与通过反相子字线信号而获得的副字线反相信号连接，第一NMOS晶体管的源极与第一负电压连接。单个主字线信号连接到第一PMOS晶体管的栅极和第一NMOS晶体管的栅极，并且子字线信号与第二NMOS晶体管的栅极连接。

50. 发明授权

US06452844B2 Semiconductor storage device having redundancy circuit for replacement of defect cells under tests 有权
标题翻译：具有冗余电路的半导体存储装置，用于更换被测试的缺陷单元
公开(公告)号：US06452844B2
公开(公告)日：2002-09-17
申请号：US09739490
申请日：2000-12-18
申请人： Yasuji Koshikawa
发明人： Yasuji Koshikawa
IPC分类号： G11C700
CPC分类号： G11C29/72 , G11C29/40
摘要： A semiconductor storage device such as a DRAM is configured to enable testing on defectiveness of memory cells by an existing memory tester, which locates defect cells to be replaced with redundancy cells by a redundancy circuit. Herein, a write circuit writes multiple-bit data to memory cells of a memory cell array under testing. Then, the multiple-bit data are read from the memory cell array by a read circuit and are compared with original one to make decisions of “pass” or “fail” on the memory cells by the memory tester. Specifically, the read circuit is configured by plural pairs of a data output circuit and a data compression circuit with respect to plural sets of prescribed data each of which consists of a prescribed number of bits corresponding to prescribed memory cells which are subjected to simultaneous replacement. The data compression circuit is configured by an exclusive-or circuit that compresses a certain type of the prescribed data to specific data having a specific logical value. Or, the data compression circuit is configured using two exclusive-or circuits that compress different types of the prescribed data to specific data. The specific data is forwarded as single-bit data, based on which the memory tester makes decisions of “pass” or “fail” on the memory cells corresponding to bits of the prescribed data being read out.
摘要翻译：诸如DRAM的半导体存储装置被配置为能够通过现有存储器测试器对存储器单元的缺陷进行测试，该存储器测试器通过冗余电路定位要被冗余单元替换的缺陷单元。这里，写入电路将多位数据写入被测试的存储单元阵列的存储单元。然后，通过读取电路从存储单元阵列中读取多位数据，并将其与原始数据进行比较，以通过存储器测试器对存储器单元进行“通过”或“失败”判定。具体地，读取电路由多对数据输出电路和数据压缩电路构成，该数据输出电路和数据压缩电路相对于多组规定数据构成，每组规定数据由对应于同时替换的规定存储器单元的规定数量的位组成。数据压缩电路由将特定类型的规定数据压缩到具有特定逻辑值的特定数据的异或电路配置。或者，数据压缩电路使用将不同类型的规定数据压缩到特定数据的两个专用或电路来配置。特定数据作为单位数据转发，基于此，存储器测试器对与读出的规定数据的位对应的存储单元进行“通过”或“失败”判定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式