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1. 发明授权

US07417908B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07417908B2
公开(公告)日：2008-08-26
申请号：US10564626
申请日：2004-07-13
申请人： Sumio Ogawa , Yasuji Koshikawa
发明人： Sumio Ogawa , Yasuji Koshikawa
IPC分类号： G11C7/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

2. 发明授权

US07613056B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07613056B2
公开(公告)日：2009-11-03
申请号：US12171081
申请日：2008-07-10
申请人： Sumio Ogawa , Yasuji Koshikawa
发明人： Sumio Ogawa , Yasuji Koshikawa
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired.The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

3. 发明申请

US20060227588A1 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US20060227588A1
公开(公告)日：2006-10-12
申请号：US10564626
申请日：2004-07-13
申请人： Sumio Ogawa , Yasuji Koshikawa
发明人： Sumio Ogawa , Yasuji Koshikawa
IPC分类号： G11C19/00
CPC分类号： G11C29/808
摘要： In a semiconductor memory device provided with a redundancy circuit for conducting a repair of defective memory cells, the memory cell defects which are unevenly distributed can be efficiently repaired. The semiconductor memory device has a plurality of memory blocks, and the memory block includes a plurality of segments. A redundancy memory block which substitutes for defective data of a segment is physically provided to each of the plurality of memory blocks. A block address of the redundancy memory block is logically allocated to the plurality of memory blocks in common.
摘要翻译：在设置有用于对缺陷存储单元进行修复的冗余电路的半导体存储器件中，可以有效地修复不均匀分布的存储单元缺陷。半导体存储器件具有多个存储块，并且存储块包括多个段。代替段的缺陷数据的冗余存储块物理地提供给多个存储块中的每一个。冗余存储器块的块地址被共同地逻辑地分配给多个存储器块。

4. 发明授权

US06349240B2 Semiconductor device manufacturing system and method of manufacturing semiconductor devices 有权
标题翻译：半导体器件制造系统和半导体器件的制造方法
公开(公告)号：US06349240B2
公开(公告)日：2002-02-19
申请号：US09814871
申请日：2001-03-23
申请人： Sumio Ogawa , Minoru Ueki , Shinichi Hara
发明人： Sumio Ogawa , Minoru Ueki , Shinichi Hara
IPC分类号： G06F1900
CPC分类号： H01L22/20 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.
摘要翻译：提供了一种半导体器件制造系统，其中读取芯片位置信息而不从包装中去除树脂，从而可以快速识别和去除故障的原因，并且可以快速提高芯片的产量。替换地址读取装置从在半导体器件被封装到封装中之后执行的测试中被确定为有故障的半导体器件中读取冗余地址。芯片位置分析装置从这些冗余地址的组合估计有缺陷的半导体器件的批号，晶片号和芯片数。故障分布映射设备根据这样获得的数据，对批次中每个晶片中的故障芯片的分布进行映射。故障原因确定装置基于上述分布来识别哪个制造装置或处理步骤已经导致晶片过程中的故障。

5. 发明授权

US07359263B2 Chip information managing method, chip information managing system, and chip information managing program 有权
标题翻译：芯片信息管理方法，芯片信息管理系统和芯片信息管理程序
公开(公告)号：US07359263B2
公开(公告)日：2008-04-15
申请号：US11440181
申请日：2006-05-25
申请人： Sumio Ogawa
发明人： Sumio Ogawa
IPC分类号： G11C7/00
CPC分类号： G11C29/838 , G11C11/401 , G11C29/783 , G11C2029/4402
摘要： In replacing word lines having defective addresses with redundant word lines, information is held in a relationship between the word lines and the redundant word lines. In other words, information is held in a replacement rule. With this arrangement, information such as a lot number, a wafer number within the lot, and a position of a chip within the wafer can be held in the chip, without increasing the chip area at all and without using a large database.
摘要翻译：在用冗余字线替换具有不良地址的字线时，信息被保持在字线和冗余字线之间的关系中。换句话说，信息保存在替换规则中。利用这种布置，不需要增加芯片面积而不使用大的数据库，可以将芯片中的批号，批次内的晶片数和晶片内的芯片的位置等信息保存在芯片中。

6. 发明授权

US5570318A Semiconductor memory device incorporating redundancy memory cells 失效
标题翻译：结合冗余存储单元的半导体存储器件
公开(公告)号：US5570318A
公开(公告)日：1996-10-29
申请号：US563940
申请日：1995-11-29
申请人： Sumio Ogawa
发明人： Sumio Ogawa
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , H04Q3/00
CPC分类号： G11C29/806 , H04Q3/0029
摘要： In a semiconductor memory device including a plurality of memory cell clocks each having a mormal memory cell array and first and second redundancy memory cell rows, one first redundancy row selecting circuit is provided for each of the memory cell blocks to access the first redundancy memory cell row upon receipt of a respective memory cell block selection signal, and one second redundancy row selecting circuit is provided for at least two of the memory cell blocks to access the second redundancy memory cell row upon receipt of a respective memory cell block selection signal.
摘要翻译：在包括具有正常存储单元阵列和第一和第二冗余存储单元行的多个存储单元时钟的半导体存储器件中，为每个存储单元块提供一个第一冗余行选择电路以访问第一冗余存储单元并且在接收到相应的存储单元块选择信号时，为至少两个存储单元块提供一个第二冗余行选择电路以访问第二冗余存储单元行。

7. 发明授权

US5371707A Dynamic random access memory device equipped with dummy cells implemented by enhancement type transistors 失效
标题翻译：配备有由增强型晶体管实现的虚拟单元的动态随机存取存储器件
公开(公告)号：US5371707A
公开(公告)日：1994-12-06
申请号：US10162
申请日：1993-01-28
申请人： Sumio Ogawa
发明人： Sumio Ogawa
IPC分类号： G11C11/4099 , G11C7/00
CPC分类号： G11C11/4099
摘要： A shared sense amplifier circuit incorporated in a dynamic random access memory device is coupled at input/output nodes with dummy cells implemented by n-channel enhancement type field effect transistors for pulling one of the input/output nodes down upon access to one of the memory cells, and one of the enhancement type dummy cells rapidly turns off so that undershoot takes place at the associated input/output node due to channel resistance between the shared sense amplifier circuit and a bit line pair, thereby enlarging differential voltage applied between the input/output nodes of the shared sense amplifier circuit.
摘要翻译：结合在动态随机存取存储器件中的共享读出放大器电路在输入/输出节点处与由n沟道增强型场效应晶体管实现的虚拟单元耦合，用于在访问存储器之一时向下拉输入/输出节点之一单元，并且增强型虚拟单元之一快速关闭，使得由于共享读出放大器电路和位线对之间的沟道电阻而在相关联的输入/输出节点处发生下冲，从而扩大了施加在输入/ 共享读出放大器电路的输出节点。

8. 发明授权

US07755163B2 Antifuse element and semiconductor device including same 失效
标题翻译：防漏元件和包括其的半导体器件
公开(公告)号：US07755163B2
公开(公告)日：2010-07-13
申请号：US12219587
申请日：2008-07-24
申请人： Sumio Ogawa
发明人： Sumio Ogawa
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown.
摘要翻译：为了提供一种反熔丝元件，其包括栅极电极，耗尽沟道区域，栅极电极和沟道区域之间的栅极绝缘膜，以及形成与沟道区域的结的扩散层区域。从平面图看，栅电极的一端大致与沟道区域和扩散层区域之间的边界重合，并以Z字形构成。栅电极的端部比线状构造的端部长，栅极绝缘膜的端部容易受到击穿。

9. 发明授权

US07054705B2 Method of manufacturing semiconductor devices 有权
公开(公告)号：US07054705B2
公开(公告)日：2006-05-30
申请号：US10044964
申请日：2002-01-15
申请人： Sumio Ogawa , Minoru Ueki , Shinichi Hara
发明人： Sumio Ogawa , Minoru Ueki , Shinichi Hara
IPC分类号： G06F19/00
CPC分类号： H01L22/20 , H01L2924/0002 , Y10T29/41 , H01L2924/00
摘要： A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.

10. 发明授权

US5318329A Flexible joint for an exhaust pipe 失效
标题翻译：用于排气管的柔性接头
公开(公告)号：US5318329A
公开(公告)日：1994-06-07
申请号：US896179
申请日：1992-06-10
申请人： Kenji Suzuki , Sumio Ogawa , Sunao Sakamoto
发明人： Kenji Suzuki , Sumio Ogawa , Sunao Sakamoto
IPC分类号： F01N13/18 , F16L27/08 , F16L39/04 , F16L27/00
CPC分类号： F01N13/1816 , F01N13/1811 , F16L27/0857 , F16L39/04
摘要： A flexible joint has a bellows, a first support cover connected with one end of the bellows, a second support cover connected with another end of the bellows, a pin fixed to the first support cover, a cap fixed to the second support cover, and a buffer member constructed of wire mesh and disposed between the first support cover in combination with the pin and the second support cover in combination with the cap. The buffer member includes two portions different in modulus of elasticity. Due to the structure, gap generation between the first support cover combined with the pin and the second support cover combined with the cap is prevented.
摘要翻译：柔性接头具有波纹管，与波纹管的一端连接的第一支撑盖，与波纹管的另一端连接的第二支撑盖，固定到第一支撑盖的销，固定到第二支撑盖的盖，以及缓冲构件，其由金属丝网构成，并且与所述盖组合地设置在所述第一支撑盖与所述销和所述第二支撑盖的组合之间。缓冲构件包括两个不同弹性模量的部分。由于结构，防止了与销的第一支撑盖和与盖组合的第二支撑盖之间的间隙产生。

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