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41. 发明授权

US5436483A Semiconductor integrated circuit device having a first MISFET of an output buffer circuit and a second MISFET of an internal circuit 失效
标题翻译：具有输出缓冲电路的第一MISFET和内部电路的第二MISFET的半导体集成电路器件
公开(公告)号：US5436483A
公开(公告)日：1995-07-25
申请号：US142965
申请日：1993-10-29
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

42. 发明授权

US5426603A Dynamic RAM and information processing system using the same 失效
标题翻译：动态RAM和信息处理系统使用相同
公开(公告)号：US5426603A
公开(公告)日：1995-06-20
申请号：US186460
申请日：1994-01-25
申请人： Masayuki Nakamura , Takayuki Kawahara , Kazuhiko Kajigaya , Kazuyoshi Oshima , Tsugio Takahashi , Hiroshi Otori , Tetsuro Matsumoto
发明人： Masayuki Nakamura , Takayuki Kawahara , Kazuhiko Kajigaya , Kazuyoshi Oshima , Tsugio Takahashi , Hiroshi Otori , Tetsuro Matsumoto
IPC分类号： G11C11/4091 , G11C11/4097 , G11C11/24
CPC分类号： G11C11/4097 , G11C11/4091
摘要： A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.
摘要翻译：使用读出放大器提供动态RAM来补偿成对MOSFET的特性差异。利用这种布置，位线的寄生电容可以增加到存储器单元的电容的至少20倍。每个位线由开关MOSFET二等分，并根据需要断开。提供了多组存储器阵列，每组存储器阵列包括用于互连连接读出放大器的公共源极线的开关MOSFET。这允许回收公共源线的电荷。

43. 发明授权

US5068712A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5068712A
公开(公告)日：1991-11-26
申请号：US409332
申请日：1989-09-19
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/31 , H01L23/495 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H01L24/32 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/05 , H01L24/06 , H01L25/105 , H01L29/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/06136 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/73215 , H01L2224/85205 , H01L2224/8592 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , Y10T29/49121
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要翻译：由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小杂散容量，提高信号传输速率和减少电气噪声。

44. 发明授权

US4887237A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4887237A
公开(公告)日：1989-12-12
申请号：US174974
申请日：1988-03-29
申请人： Tetsuro Matsumoto
发明人： Tetsuro Matsumoto
IPC分类号： G11C11/404 , H01L27/108
CPC分类号： G11C11/404 , H01L27/10805
摘要： A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electrodes and a dielectric film which includes a silicon nitride film existing between the pair of electrodes. One electrode of the capacitor is provided with a terminal to which a voltage is applied. The value of the applied voltage is chosen so that the voltage applied between the pair of electrodes is smaller in an absolute value than a voltage applied to the bit line.
摘要翻译：半导体存储器件设置有存储单元，每个存储单元包括彼此串联并连接到位线的绝缘栅型场效应晶体管和电容器。电容器由一对电极和介电膜组成，电介质膜包括存在于该对电极之间的氮化硅膜。电容器的一个电极设置有施加电压的端子。选择施加电压的值，使得在一对电极之间施加的电压的绝对值小于施加到位线的电压的绝对值。

45. 发明授权

US4562555A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4562555A
公开(公告)日：1985-12-31
申请号：US535232
申请日：1983-09-23
申请人： Yoshiaki Ouchi , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa
发明人： Yoshiaki Ouchi , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C8/04
CPC分类号： G11C7/10 , G11C7/1033 , G11C8/04
摘要： An address multiplex type system for a dynamic RAM includes a memory cell array having a plurality of memory cells which are simultaneously selected by signals output from an address decoder, a decoder, and a shift register. The dynamic RAM further includes a selecting circuit which receives a plurality of address signals applied externally through one of a plurality of pins of a package in a time-sharing manner and makes it possible to write or read data into or from one memory cell of the plurality of memory cells selected. The dynamic RAM can read out or write in serially data of a plurality of memory cells selected from the memory cell array when a shift register operates. The dynamic RAM can also read or write data serially into or from a plurality of memory cells selected from the memory cell array simply by connecting the pin to a predetermined potential. When the data is written or read serially, the pin arrangement of the package of a 256K bit dynamic RAM can be substantially the same as that of the package of a 64K bit dynamic RAM. Hence, compatibility can be established between the 256K bit dynamic RAM and a 64K bit dynamic RAM.
摘要翻译：用于动态RAM的地址多路复用类型系统包括具有多个存储单元的存储单元阵列，这些存储单元通过从地址解码器，解码器和移位寄存器输出的信号同时选择。动态RAM还包括选择电路，其以分时方式接收通过封装的多个引脚之一施加到外部的多个地址信号，并且使得可以将数据写入或从其中的一个存储器单元读取数据选择多个存储单元。当移位寄存器操作时，动态RAM可以读出或写入从存储单元阵列中选择的多个存储单元的串行数据。动态RAM也可以简单地通过将引脚连接到预定电位，来将数据串行读取或写入从存储单元阵列中选择的多个存储单元中。当数据被串行写入或读取时，256K位动态RAM的封装的引脚排列可以与64K位动态RAM的封装基本相同。因此，可以在256K位动态RAM和64K位动态RAM之间建立兼容性。

46. 发明授权

US06303982B2 Semiconductor device 失效
公开(公告)号：US06303982B2
公开(公告)日：2001-10-16
申请号：US09771617
申请日：2001-01-30
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L23495
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , H01L2924/00012 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/0695 , H01L2224/85399
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

47. 发明授权

US6100580A Semiconductor device having all outer leads extending from one side of a resin member 失效
标题翻译：具有从树脂构件的一侧延伸的所有外部引线的半导体装置
公开(公告)号：US6100580A
公开(公告)日：2000-08-08
申请号：US167736
申请日：1998-10-07
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/31 , H01L23/495 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H01L24/32 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/05 , H01L24/06 , H01L25/105 , H01L29/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/06136 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/73215 , H01L2224/85205 , H01L2224/8592 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , Y10T29/49121
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要翻译：由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小杂散容量，提高信号传输速率和减少电气噪声。

48. 发明授权

US5610089A Method of fabrication of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件制造方法
公开(公告)号：US5610089A
公开(公告)日：1997-03-11
申请号：US429868
申请日：1995-04-27
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78
CPC分类号： H01L27/10873 , H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L29/78 , H01L29/7836
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implanation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

49. 发明授权

US5534723A Semiconductor integrated circuit device having output and internal circuit MISFETS 失效
标题翻译：具有输出和内部电路MISFETS的半导体集成电路器件
公开(公告)号：US5534723A
公开(公告)日：1996-07-09
申请号：US431568
申请日：1995-04-27
申请人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
发明人： Hidetoshi Iwai , Kazumichi Mitsusada , Masamichi Ishihara , Tetsuro Matsumoto , Kazuyuki Miyazawa , Hisao Katto , Kousuke Okuyama
IPC分类号： H01L21/8238 , H01L21/8242 , H01L27/02 , H01L27/092 , H01L29/78 , H01L29/06
CPC分类号： H01L21/823864 , H01L27/0251 , H01L27/0266 , H01L27/0922 , H01L27/10873 , H01L29/78
摘要： Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region. As a further embodiment of the present invention, a semiconductor integrated circuit device is provided wherein the source and drain regions of an MOSFET in the internal circuit have lightly doped drain (LDD) structure in order to suppress the appearance of hot carriers, and the source and drain regions of an MOSFET in the input/output circuit have structure doped with phosphorus at a high impurity concentration, in order to enhance an electrostatic breakdown voltage.
摘要翻译：公开了具有被静电保护电路保护的内部电路的半导体器件，内部电路和静电保护电路形成在同一半导体衬底上。内部电路包括MIS元件，并具有双扩散漏极结构，而保护电路具有单扩散漏极结构。内部电路可以是例如DRAM，并且保护电路可以具有扩散电阻器和钳位MIS元件。单扩散漏极结构可以形成在半导体衬底上的保护电路中，同时通过以下步骤在同一衬底上的内部电路中提供双扩散漏极结构：（1）扫描离子注入装置以避免离子注入第一离子进入保护电路的区域，和/或（2）在保护电路的区域上形成光致抗蚀剂膜，以防止第一离子离子注入保护电路区域。作为本发明的另一实施例，提供了一种半导体集成电路器件，其中内部电路中的MOSFET的源极和漏极区域具有轻掺杂漏极（LDD）结构，以便抑制热载流子的出现，源极并且输入/输出电路中的MOSFET的漏极区域掺杂有高杂质浓度的磷的结构，以增强静电击穿电压。

50. 发明授权

US4740920A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4740920A
公开(公告)日：1988-04-26
申请号：US925223
申请日：1986-10-31
申请人： Tetsuro Matsumoto
发明人： Tetsuro Matsumoto
IPC分类号： G11C11/404 , H01L27/108 , G11C11/40
CPC分类号： G11C11/404 , H01L27/10805
摘要： A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electrodes and a dielectric film which includes a silicon nitride film existing between the pair of electrodes. One electrode of the capacitor is provided with a terminal to which a voltage is applied. The value of the applied voltage is chosen so that the voltage applied between the pair of electrodes is smaller in an absolute value than a voltage applied to the bit line.
摘要翻译：半导体存储器件设置有存储单元，每个存储单元包括彼此串联并连接到位线的绝缘栅型场效应晶体管和电容器。电容器由一对电极和介电膜组成，电介质膜包括存在于该对电极之间的氮化硅膜。电容器的一个电极设置有施加电压的端子。选择施加电压的值，使得在一对电极之间施加的电压的绝对值小于施加到位线的电压的绝对值。

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