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41. 发明授权

US07876627B2 Semiconductor memory device having a sense amplifier circuit with decreased offset 有权
标题翻译：半导体存储器件具有具有减小的偏移的读出放大器电路
公开(公告)号：US07876627B2
公开(公告)日：2011-01-25
申请号：US11969223
申请日：2008-01-03
申请人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：具有高集成度，低功耗和高操作速度的半导体存储器件。存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

42. 发明授权

US07842976B2 Semiconductor device having MOS transistors which are serially connected via contacts and conduction layer 有权
标题翻译：具有通过触点和导电层串联连接的MOS晶体管的半导体器件
公开(公告)号：US07842976B2
公开(公告)日：2010-11-30
申请号：US12259527
申请日：2008-10-28
申请人： Isamu Fujii , Shinichi Miyatake , Yuko Watanabe , Homare Sato
发明人： Isamu Fujii , Shinichi Miyatake , Yuko Watanabe , Homare Sato
IPC分类号： H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L27/0207 , H01L27/10885
摘要： A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes.
摘要翻译：半导体器件包括以预定间距排列的多条信号线; 连接到信号线的第一和第二MOS晶体管，并且彼此串联连接; 以及连接装置，其作为串联连接的第一和第二MOS晶体管之间的连接节点，并且将第一和第二MOS晶体管之一的源极区域连接到第一和第二MOS晶体管的另一个的漏极区域，经由通过绝缘层形成的接触孔和连接到接触孔的导电层。

43. 发明申请

US20100244936A1 Semiconductor device having a complementary field effect transistor 失效
标题翻译：具有互补场效应晶体管的半导体器件
公开(公告)号：US20100244936A1
公开(公告)日：2010-09-30
申请号：US12662038
申请日：2010-03-29
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： G05F1/10
CPC分类号： H03K19/00361 , H03K19/0008 , H03K2217/0018
摘要： A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.
摘要翻译：半导体器件防止互补场效应晶体管的截止电流随着环境温度的变化而变化。半导体器件包括：衬底电压产生电路，其产生形成CMOS的n沟道MOS晶体管的衬底电压; 复制晶体管，其是n沟道MOS晶体管的复制品，并且是二极管连接的; 以及在复制晶体管的阳极和阴极之间施加预定电压值的电压的施加电压器。在该半导体器件中，复制晶体管的衬底电压是由衬底电压产生电路产生的衬底电压。衬底电压产生电路控制要产生的衬底电压，使得流入复制晶体管的电流的电流值等于给定的目标值。

44. 发明授权

US07609572B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07609572B2
公开(公告)日：2009-10-27
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译：在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低感觉速度增加。因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

45. 发明申请

US20080067551A1 Semiconductor device having pseudo power supply wiring and method of designing the same 审中-公开
标题翻译：具有伪电源布线的半导体装置及其设计方法
公开(公告)号：US20080067551A1
公开(公告)日：2008-03-20
申请号：US11898155
申请日：2007-09-10
申请人： Yoshiro Riho , Ken Ota , Hiromasa Noda , Shinichi Miyatake
发明人： Yoshiro Riho , Ken Ota , Hiromasa Noda , Shinichi Miyatake
IPC分类号： H01L27/105 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78 , H01L23/5286 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： Inverters are connected between a pseudo power supply wiring and a main power supply wiring, while inverters are connected between a main power supply wiring VDD and a pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Even if improper connections are found or logical changes are required, the connection destination of the source is switched easily.
摘要翻译：逆变器连接在伪电源线和主电源配线之间，而逆变器连接在主电源线VDD和伪电源配线之间。连接到晶体管的源极的是用于切换到主电源布线或伪电源布线的开关区域。连接到晶体管的源极的是用于切换到主电源布线或伪电源布线的开关区域。即使发现不正确的连接或需要进行逻辑更改，源的连接目的地也很容易切换。

46. 发明申请

US20070147152A1 Sense amplifier for semiconductor memory device 有权
标题翻译：用于半导体存储器件的检测放大器
公开(公告)号：US20070147152A1
公开(公告)日：2007-06-28
申请号：US11706409
申请日：2007-02-15
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
摘要翻译：本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

47. 发明授权

US06178108B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06178108B1
公开(公告)日：2001-01-23
申请号：US09258462
申请日：1999-02-26
申请人： Shinichi Miyatake , Shigekazu Kase , Masayuki Nakamura , Masatoshi Hasegawa , Kazuhiko Kajigaya
发明人： Shinichi Miyatake , Shigekazu Kase , Masayuki Nakamura , Masatoshi Hasegawa , Kazuhiko Kajigaya
IPC分类号： G11C1124
CPC分类号： G11C11/22
摘要： In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by detecting indirect that the plate voltage has reached the predetermined potential near the intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging the pair bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.
摘要翻译：在具有多个存储单元的半导体存储器件中，其中每个存储单元由地址选择MOSFET和信息存储电容器形成，并且由中间电位构成的板电压被提供给信息存储电容器的公共电极，通过检测间接使用电压检测电路或定时器电路使板电压达到中间电位附近的预定电位来启用存储器访问，当板的电压被抑制时，字线的选择操作或预先充电到中间电位电压低于预定电位，然后在板电压达到预定电位后取消上述禁止条件。

48. 发明授权

US5970003A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5970003A
公开(公告)日：1999-10-19
申请号：US84251
申请日：1998-05-26
申请人： Shinichi Miyatake , Shuuichi Kubouchi
发明人： Shinichi Miyatake , Shuuichi Kubouchi
IPC分类号： G11C11/401 , G11C11/407 , G11C17/16 , G11C29/00 , G11C29/04 , H01L21/82 , G11C7/00
CPC分类号： G11C29/80 , G11C17/16 , G11C29/812
摘要： A semiconductor memory device comprising at least one memory mat comprised of a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines respectively intersect a plurality of bit lines and spare bit lines placed so as to intersect the word lines and spare word lines. In the semiconductor memory device, a plurality of fuse means allowed to open or remain unopen in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines are used to control gate means based on their corresponding complementary signals. Thus, the gate means transmit signals for selecting their corresponding word lines or bit lines to thereby produce coincidence/non-coincidence signals.
摘要翻译：一种半导体存储器件，包括至少一个由多个存储器单元组成的存储垫，所述多个存储单元分别设置在多个字线和备用字线分别与多个位线相交的位置和与字线相交的备用位线和备用字线。在半导体存储器件中，根据存储的关于用于指定缺陷字线或缺陷位线的地址编码的信息，允许许多熔丝装置打开或保持未打开，以便基于它们对应的互补信号来控制栅极装置。因此，门装置发送用于选择它们对应的字线或位线的信号，从而产生符合/非重合信号。

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