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1. 发明申请

US20080181026A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080181026A1
公开(公告)日：2008-07-31
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/08
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译：在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低感觉速度增加。因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

2. 发明授权

US07609572B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07609572B2
公开(公告)日：2009-10-27
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译：在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低感觉速度增加。因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

3. 发明授权

US07995405B2 Semiconductor memory device having a sense amplifier circuit with decreased offset 有权
公开(公告)号：US07995405B2
公开(公告)日：2011-08-09
申请号：US12967728
申请日：2010-12-14
申请人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

4. 发明授权

US07876627B2 Semiconductor memory device having a sense amplifier circuit with decreased offset 有权
标题翻译：半导体存储器件具有具有减小的偏移的读出放大器电路
公开(公告)号：US07876627B2
公开(公告)日：2011-01-25
申请号：US11969223
申请日：2008-01-03
申请人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：具有高集成度，低功耗和高操作速度的半导体存储器件。存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

5. 发明申请

US20110079858A1 SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET 有权
标题翻译：具有放大偏差的感测放大器电路的半导体存储器件
公开(公告)号：US20110079858A1
公开(公告)日：2011-04-07
申请号：US12967728
申请日：2010-12-14
申请人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： H01L27/108
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：具有高集成度，低功耗和高操作速度的半导体存储器件。存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

6. 发明申请

US20080175084A1 SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER CIRCUIT 有权
标题翻译：半导体存储器件和感测放大器电路
公开(公告)号：US20080175084A1
公开(公告)日：2008-07-24
申请号：US11969223
申请日：2008-01-03
申请人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：一种具有高集成度，低功耗和高运行速度的半导体存储器件，包括具有多个下拉电路和上拉电路的读出放大器电路，其中构成多个下拉电路中的一个的晶体管具有比构成其他下拉电路的晶体管（例如沟道长度和沟道宽度）的常数大的常数，在多个下拉电路中具有较大的晶体管常数的下拉电路先前被激活，然后另一个下拉电路和上拉电路被激活以进行读取，此外，数据线和先前驱动的下拉电路通过NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制激活或下拉电路失活。

7. 发明授权

US07633833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07633833B2
公开(公告)日：2009-12-15
申请号：US12028788
申请日：2008-02-09
申请人： Riichiro Takemura , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
发明人： Riichiro Takemura , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译：根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

8. 发明申请

US20080239865A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080239865A1
公开(公告)日：2008-10-02
申请号：US12028788
申请日：2008-02-09
申请人： Riichiro TAKEMURA , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
发明人： Riichiro TAKEMURA , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译：根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

9. 发明申请

US20090180341A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090180341A1
公开(公告)日：2009-07-16
申请号：US12314860
申请日：2008-12-17
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： G11C7/00 , H03L7/06 , G11C8/18
CPC分类号： G11C7/22 , G11C7/04 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C7/222 , G11C11/4094 , H01L27/0207 , H01L27/108 , H01L27/10897 , H03K5/15066
摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).
摘要翻译：公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。定时寄存器保存m和n的值。这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

10. 发明授权

US07973582B2 Timing control circuit and semiconductor storage device 有权
标题翻译：定时控制电路和半导体存储设备
公开(公告)号：US07973582B2
公开(公告)日：2011-07-05
申请号：US12205668
申请日：2008-09-05
申请人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
发明人： Akira Ide , Yasuhiro Takai , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Hiroaki Nakaya
IPC分类号： H03H11/26
CPC分类号： H03K5/15033
摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.
摘要翻译：公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号从第一时钟的上升沿开始约td = m·T1 + n·（T2 / L）的延迟td，其中m和n是非负整数。定时控制电路具有粗略延迟电路和精细延迟电路。粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m·T1的粗略定时信号。精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n·（T2 / L）的精细定时信号。 m和n的值可以由寄存器设置。

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