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41. 发明申请

US20080018218A1 Straddling and supporting structure for a field emission display device and a manufacturing method thereof 审中-公开
标题翻译：场致发射显示装置的跨接支撑结构及其制造方法
公开(公告)号：US20080018218A1
公开(公告)日：2008-01-24
申请号：US11491123
申请日：2006-07-24
申请人： Wei-Sheng Hsu , Cheng-Chieh Kao , Yi-Jung Chung
发明人： Wei-Sheng Hsu , Cheng-Chieh Kao , Yi-Jung Chung
IPC分类号： H01J1/62 , H01J9/24 , H01J1/88
CPC分类号： H01J29/90 , H01J9/241 , H01J9/28 , H01J29/862
摘要： A straddling and supporting structure for a field emission display device and a manufacturing method thereof is disclosed. The present invention provides a supporting structure that straddles across electrodes to provide a straddling structure for the conducting lines between the electrodes to shorten the conducting path, and can be used as a vacuum supporting structure between the cathode substrate and the anode substrate.
摘要翻译：公开了一种用于场致发射显示装置的跨接和支撑结构及其制造方法。本发明提供跨越电极的支撑结构，以提供用于电极之间的导线的跨接结构，以缩短导电路径，并且可以用作阴极基板和阳极基板之间的真空支撑结构。

42. 外观设计

USD559777S1 Power supply 有权
标题翻译：电源
公开(公告)号：USD559777S1
公开(公告)日：2008-01-15
申请号：US29268116
申请日：2006-10-31
申请人： Chih-Ming Hu , Sheng-Hsu Ho , Ching-Wen Huang , Shih-An Liang
设计人： Chih-Ming Hu , Sheng-Hsu Ho , Ching-Wen Huang , Shih-An Liang

43. 发明申请

US20070284575A1 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US20070284575A1
公开(公告)日：2007-12-13
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L29/12
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

44. 发明申请

US20070170536A1 Liquid phase epitaxial GOI photodiode with buried high resistivity germanium layer 审中-公开
标题翻译：液相外延GOI光电二极管，埋置高电阻率锗层
公开(公告)号：US20070170536A1
公开(公告)日：2007-07-26
申请号：US11339011
申请日：2006-01-25
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1055 , H01L31/1808 , H01L31/1872 , Y02E10/50
摘要： A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.
摘要翻译：提供了一种用于制造具有埋置的高电阻率锗（Ge）层的液相外延（LPE）绝缘体锗绝缘体（GOI）光电二极管的器件和相关方法。该方法提供硅（Si）衬底，并且形成具有Si种子存取区域的覆盖Si衬底的底部绝缘体。然后，形成具有n +掺杂（n +）台面，p +掺杂（p +）Ge底部绝缘体界面和台面侧面界面的Ge P-I-N二极管，以及插入在p + Ge和n + Ge之间的高电阻率Ge层。在p + Ge侧面界面的区域上形成金属电极，形成覆盖n + Ge台面的透明电极。在一个方面，该方法沉积覆盖高电阻率Ge层的氮化硅层临时盖，并进行退火以使Ge底界面和高电阻率Ge层外延结晶。

45. 发明申请

US20070167008A1 Nanotip electrode non-volatile memory resistor cell 审中-公开
标题翻译：纳米电极非易失性存储电阻单元
公开(公告)号：US20070167008A1
公开(公告)日：2007-07-19
申请号：US11717818
申请日：2007-03-14
申请人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
发明人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
IPC分类号： H01L21/44
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
摘要翻译：提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

46. 发明申请

US20070141744A1 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US20070141744A1
公开(公告)日：2007-06-21
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
发明人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在天然掺杂锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火激活N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

47. 发明申请

US20070111368A1 Photovoltaic structure with a conductive nanowire array electrode 失效
标题翻译：具有导电纳米线阵列电极的光伏结构
公开(公告)号：US20070111368A1
公开(公告)日：2007-05-17
申请号：US11280423
申请日：2005-11-16
申请人： Fengyan Zhang , Robert Barrowcliff , Sheng Hsu
发明人： Fengyan Zhang , Robert Barrowcliff , Sheng Hsu
IPC分类号： H01L51/40 , H01L21/00
CPC分类号： H01L51/4213 , B82Y10/00 , H01L51/0046 , H01L51/0048 , H01L51/4226 , H01L51/4233 , H01L51/441 , Y02E10/52 , Y02E10/549
摘要： A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).
摘要翻译：提供光伏（PV）结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。该方法包括：形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型（即n型）的第一半导体层; 形成与所述第一掺杂剂类型（即，p型）相反的第二掺杂剂类型的第二半导体层，所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。第一和第二半导体层可以是诸如导电聚合物，具有富勒烯衍生物的共轭聚合物和诸如CdSe，CdS，二氧化钛或ZnO的无机材料的材料。导电纳米线可以是诸如IrO 2，In 2 O 3，SnO 2，或铟的材料氧化锡（ITO）。

48. 发明申请

US20070108502A1 Nanocrystal silicon quantum dot memory device 审中-公开
标题翻译：纳米晶硅量子点存储器件
公开(公告)号：US20070108502A1
公开(公告)日：2007-05-17
申请号：US11281955
申请日：2005-11-17
申请人： Tingkai Li , Sheng Hsu , Lisa Stecker
发明人： Tingkai Li , Sheng Hsu , Lisa Stecker
IPC分类号： H01L29/788 , H01L21/336 , G11C16/04
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/349 , G11C16/3495 , G11C2216/08 , H01L29/15 , H01L29/40114 , H01L29/42324 , H01L29/4925 , H01L29/66825
摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).
摘要翻译：已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。

49. 发明申请

US20070015330A1 Metal/semiconductor/metal (MSM) back-to-back Schottky diode 有权
标题翻译：金属/半导体/金属（MSM）背对背肖特基二极管
公开(公告)号：US20070015330A1
公开(公告)日：2007-01-18
申请号：US11435669
申请日：2006-05-17
申请人： Tingkai Li , Sheng Hsu , David Evans
发明人： Tingkai Li , Sheng Hsu , David Evans
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

50. 发明申请

US20070015328A1 MSM binary switch memory device 有权
公开(公告)号：US20070015328A1
公开(公告)日：2007-01-18
申请号：US11184660
申请日：2005-07-18
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

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