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41. 发明申请

WO2007021888A2 METHOD AND SYSTEM FOR PROVIDING AN ENERGY EFFICIENT REGISTER FILE 审中-公开
标题翻译：提供能量效率寄存器文件的方法和系统
公开(公告)号：WO2007021888A2
公开(公告)日：2007-02-22
申请号：PCT/US2006031298
申请日：2006-08-09
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , BRIDGES JEFFREY TODD , MCILVAINE MICHAEL SCOTT , BURDA GREGORY CHRISTOPHER
发明人： DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , BRIDGES JEFFREY TODD , MCILVAINE MICHAEL SCOTT , BURDA GREGORY CHRISTOPHER
IPC分类号： G06F9/30
CPC分类号： G06F9/30105 , G06F9/30141
摘要： A register file is disclosed. The register file includes a plurality of registers and a decoder. The decoder may be configured to receive an address for any one of the registers, and disable a read operation to the addressed register if data in the addressed register is invalid.
摘要翻译：公开了一种寄存器文件。寄存器文件包括多个寄存器和解码器。解码器可以被配置为接收任何一个寄存器的地址，并且如果寻址的寄存器中的数据无效，则禁止对寻址的寄存器的读取操作。

42. 发明申请

WO2006094196A3 METHOD AND APPARATUS FOR POWER REDUCTION IN AN HETEROGENEOUSLY- MULTI-PIPELINED PROCESSOR 审中-公开
标题翻译：多异构管道加工器中减少功率的方法和装置
公开(公告)号：WO2006094196A3
公开(公告)日：2007-02-01
申请号：PCT/US2006007607
申请日：2006-03-03
申请人： QUALCOMM INC , COLLOPY THOMAS K , SARTORIUS THOMAS ANDREW
发明人： COLLOPY THOMAS K , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor resources, such as an instruction cache, a register file stack, a data cache, a memory interface, and other architected registers within the system. In disclosed examples, the processor is controlled such that processes requiring higher performance run in the higher performance pipeline, whereas those requiring lower performance utilize the lower performance pipeline, in at least some instances while the higher performance pipeline is effectively inactive or even shut-off to minimize power consumption. The configuration of the processor at any given time, that is to say the pipeline(s) currently operating, may be controlled via several different techniques.
摘要翻译：处理器包括公共指令解码前端，例如，提取和解码阶段，以及一组异构的处理流水线。较低性能的管道具有较少的级数，并且可以利用较低速度/功率电路。更高性能的管道具有更多的阶段并且利用更快的电路。管道共享其他处理器资源，例如指令高速缓存，寄存器堆栈，数据高速缓存，存储器接口和系统内的其他架构寄存器。在所公开的示例中，处理器被控制，使得需要更高性能的处理在较高性能流水线中运行，而在较低性能流水线的那些需求较低的性能流水线中，至少在某些情况下使用较低性能流水线，而较高性能流水线有效地不活动或甚至切断以最小化功耗。处理器在任何给定时间的配置，也就是当前操作的流水线，可以通过几种不同的技术进行控制。

43. 发明申请

WO2006135590A2 METHOD AND APPARATUS FOR MANAGING INSTRUCTION FLUSHING IN A MICROPROCESSOR'S INSTRUCTION PIPELINE 审中-公开
标题翻译：用于管理微处理器指令管道中的指导性冲洗的方法和装置
公开(公告)号：WO2006135590A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/021617
申请日：2006-06-02
申请人： QUALCOMM INCORPORATED , MCILVAINE, Michael Scott , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： MCILVAINE, Michael Scott , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译：在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地从指令流水线中刷新指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新。因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令，这被标记为依赖于不正确的分支预测。

44. 发明申请

WO2006096569A3 FORWARD LOOKING BRANCH TARGET ADDRESS CACHING 审中-公开
标题翻译：前瞻性分支目标地址缓存
公开(公告)号：WO2006096569A3
公开(公告)日：2006-12-21
申请号：PCT/US2006007759
申请日：2006-03-03
申请人： QUALCOMM INC , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
发明人： SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL , DIEFFENDERFER JAMES NORRIS , BRIDGES JEFFREY TODD , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38 , G06F9/32 , G06F12/08
CPC分类号： G06F12/1063 , G06F9/321 , G06F9/3806 , G06F9/3844 , G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A pipelined processor comprises an instruction cache (iCache), a branch target address cache (BTAC), and processing stages, including a stage to fetch from the iCache and the BTAC. To compensate for the number of cycles needed to fetch a branch target address from the BTAC, the fetch from the BTAC leads the fetch of a branch instruction from the iCache by an amount related to the cycles needed to fetch from the BTAC. Disclosed examples either decrement a write address of the BTAC or increment a fetch address of the BTAC, by an amount essentially corresponding to one less than the cycles needed for a BTAC fetch.
摘要翻译：流水线处理器包括指令缓存（iCache），分支目标地址缓存（BTAC）和处理阶段，包括从iCache和BTAC中提取的阶段。为了补偿从BTAC获取分支目标地址所需的周期数，从BTAC获取从iCache获取的分支指令的数量与从BTAC获取所需的周期相关。所公开的示例或者递减BTAC的写地址或者增加BTAC的提取地址的量基本上对应于比BTAC提取所需的周期小的量。

45. 发明申请

WO2006060198A9 TRANSLATION LOOKASIDE BUFFER (TLB) ACCESS SUPRESSION FOR INTRA-PAGE PROGRAM COUNTER RELATIVE OR ABSOLUTE ADDRESS BRANCH INSTRUCTIONS 审中-公开
标题翻译：翻译LOOKASIDE BUFFER（TLB）访问权限用于内部程序计数器相对或绝对地址分支指令
公开(公告)号：WO2006060198A9
公开(公告)日：2006-12-14
申请号：PCT/US2005041998
申请日：2005-11-17
申请人： QUALCOMM INC , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
发明人： DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STEMPEL BRIAN MICHAEL
IPC分类号： G06F9/32 , G06F1/32 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA位于同一页面中，那么如BTSP位所指示的那样，对BTA的TLB访问检查权限属性被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

46. 发明申请

WO2006125220A2 HANDLING CACHE MISS IN AN INSTRUCTION CROSSING A CACHE LINE BOUNDARY 审中-公开
标题翻译：在指令中处理高速缓存中的错误交叉缓存线路边界
公开(公告)号：WO2006125220A2
公开(公告)日：2006-11-23
申请号：PCT/US2006/019789
申请日：2006-05-18
申请人： QUALCOMM INCORPORATED , STEMPEL, Brian, Michael , BRIDGES, Jeffrey, Todd , SMITH, Rodney, Wayne , SARTORIUS, Thomas, Andrew
发明人： STEMPEL, Brian, Michael , BRIDGES, Jeffrey, Todd , SMITH, Rodney, Wayne , SARTORIUS, Thomas, Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译：处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。指令可能会跨越缓存行边界。流水线处理两个地址以恢复完整的边界交叉指令。在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。

47. 发明申请

WO2006102667A2 ENFORCING STRONGLY-ORDERED REQUESTS IN A WEAKLY-ORDERED PROCESSING SYSTEM 审中-公开
标题翻译：在弱势处理系统中执行强大的要求
公开(公告)号：WO2006102667A2
公开(公告)日：2006-09-28
申请号：PCT/US2006/011174
申请日：2006-03-23
申请人： QUALCOMM INCORPORATED , HOFMANN, Richard, Gerard , SARTORIUS, Thomas, Andrew , SPEIER, Thomas, Philip , GANASAN, Jaya, Prakash, Subramaniam , DIEFFENDERFER, James, Norris , SULLIVAN, James, Edward
发明人： HOFMANN, Richard, Gerard , SARTORIUS, Thomas, Andrew , SPEIER, Thomas, Philip , GANASAN, Jaya, Prakash, Subramaniam , DIEFFENDERFER, James, Norris , SULLIVAN, James, Edward
IPC分类号： G06F13/16 , G06F9/38
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

48. 发明申请

WO2006099633A2 METHOD AND SYSTEM FOR OPTIMIZING TRANSLATION LOOKASIDE BUFFER ENTRIES 审中-公开
标题翻译：用于优化翻译缓冲区入口的方法和系统
公开(公告)号：WO2006099633A2
公开(公告)日：2006-09-21
申请号：PCT/US2006010087
申请日：2006-03-17
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , AUGSBURG VICTOR ROBERTS
发明人： SARTORIUS THOMAS ANDREW , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , AUGSBURG VICTOR ROBERTS
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.
摘要翻译：提供了一种用于优化翻译后备缓冲区条目的系统。该系统包括翻译后备缓冲器，其被配置为存储多个条目，每个条目具有大小属性，每个条目引用对应的页面，以及控制逻辑，被配置为修改翻译后备缓冲器中现有条目的大小属性，如果新的页面与现有条目引用的现有页面是连续的。修改其大小属性后的现有条目引用包含现有页面和新页面的合并页面。

49. 发明申请

WO2006096568A2 POWER SAVING METHODS AND APPARATUS TO SELECTIVELY ENABLE CACHE BITS BASED ON KNOWN PROCESSOR STATE 审中-公开
标题翻译：基于已知处理器状态的省电方法和选择性使能的缓存器的设备
公开(公告)号：WO2006096568A2
公开(公告)日：2006-09-14
申请号：PCT/US2006/007758
申请日：2006-03-03
申请人： QUALCOMM Incorporated , STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SMITH, Rodney Wayne , SARTORIUS, Thomas Andrew
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SMITH, Rodney Wayne , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

50. 发明申请

WO2006094297A1 STOP WAITING FOR SOURCE OPERAND WHEN CONDITIONAL INSTRUCTION WILL NOT EXECUTE 审中-公开
标题翻译：当条件指令不能执行时，停止等待源操作
公开(公告)号：WO2006094297A1
公开(公告)日：2006-09-08
申请号：PCT/US2006/008137
申请日：2006-03-06
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , MCILVAINE, Michael, Scott , SARTORIUS, Thomas, Andrew
发明人： DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , MCILVAINE, Michael, Scott , SARTORIUS, Thomas, Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/3001 , G06F9/30072
摘要： The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition is made. If the condition is such that the instruction will not execute on this pass through the pipeline, the hold with regard to the conditional instruction may be terminated, that is to say skipped or stopped prior to completion of receiving all the associated operand data. Flow of the non-executing instruction through the pipeline, for example, need not wait for an earlier instruction to compute and write source operand data for use by the conditional instruction.
摘要翻译：基于早期识别这种指令将不会在流水线处理器的当前通过中执行的情况下，缓解不执行条件指令的延迟，否则将等待后期操作数数据施加。在执行之前的适当时刻，作出关于条件的确定。如果条件使得该指令不能在通过流水线的该通过上执行，则关于条件指令的保持可以被终止，也就是说在完成接收所有相关联的操作数数据之前被跳过或停止。例如，通过流水线的不执行指令的流程不需要等待较早的指令来计算和写入源操作数数据以供条件指令使用。

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