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1. 发明申请

WO2006094196A2 METHOD AND APPARATUS FOR POWER REDUCTION UTILIZING HETEROGENEOUSLY- MULTI-PIPELINED PROCESSOR 审中-公开
标题翻译：用于减少异质多管道加工器的减少电力的方法和装置
公开(公告)号：WO2006094196A2
公开(公告)日：2006-09-08
申请号：PCT/US2006/007607
申请日：2006-03-03
申请人： QUALCOMM INCORPORATED , COLLOPY, Thomas K. , SARTORIUS, Thomas Andrew
发明人： COLLOPY, Thomas K. , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor resources, such as an instruction cache, a register file stack, a data cache, a memory interface, and other architected registers within the system. In disclosed examples, the processor is controlled such that processes requiring higher performance run in the higher performance pipeline, whereas those requiring lower performance utilize the lower performance pipeline, in at least some instances while the higher performance pipeline is effectively inactive or even shut-off to minimize power consumption. The configuration of the processor at any given time, that is to say the pipeline(s) currently operating, may be controlled via several different techniques.
摘要翻译：处理器包括公共指令解码前端，例如，提取和解码阶段，以及一组异构的处理流水线。较低性能的管道具有较少的级，并且可以利用较低速度/功率电路。更高性能的管道具有更多的阶段并且利用更快的电路。管道共享其他处理器资源，例如指令高速缓存，寄存器堆栈，数据高速缓存，存储器接口和系统内的其他架构寄存器。在公开的示例中，处理器被控制，使得需要更高性能的处理在较高性能流水线中运行，而那些需要较低性能的流程在至少某些情况下利用较低性能流水线，而较高性能流水线有效地不活动或甚至切断以最小化功耗。处理器在任何给定时间的配置，也就是说当前操作的流水线可以通过几种不同的技术来控制。

2. 发明申请

WO2006094196A3 METHOD AND APPARATUS FOR POWER REDUCTION IN AN HETEROGENEOUSLY- MULTI-PIPELINED PROCESSOR 审中-公开
标题翻译：多异构管道加工器中减少功率的方法和装置
公开(公告)号：WO2006094196A3
公开(公告)日：2007-02-01
申请号：PCT/US2006007607
申请日：2006-03-03
申请人： QUALCOMM INC , COLLOPY THOMAS K , SARTORIUS THOMAS ANDREW
发明人： COLLOPY THOMAS K , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor resources, such as an instruction cache, a register file stack, a data cache, a memory interface, and other architected registers within the system. In disclosed examples, the processor is controlled such that processes requiring higher performance run in the higher performance pipeline, whereas those requiring lower performance utilize the lower performance pipeline, in at least some instances while the higher performance pipeline is effectively inactive or even shut-off to minimize power consumption. The configuration of the processor at any given time, that is to say the pipeline(s) currently operating, may be controlled via several different techniques.
摘要翻译：处理器包括公共指令解码前端，例如，提取和解码阶段，以及一组异构的处理流水线。较低性能的管道具有较少的级数，并且可以利用较低速度/功率电路。更高性能的管道具有更多的阶段并且利用更快的电路。管道共享其他处理器资源，例如指令高速缓存，寄存器堆栈，数据高速缓存，存储器接口和系统内的其他架构寄存器。在所公开的示例中，处理器被控制，使得需要更高性能的处理在较高性能流水线中运行，而在较低性能流水线的那些需求较低的性能流水线中，至少在某些情况下使用较低性能流水线，而较高性能流水线有效地不活动或甚至切断以最小化功耗。处理器在任何给定时间的配置，也就是当前操作的流水线，可以通过几种不同的技术进行控制。

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