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1. 发明申请

WO2006057907A2 PRE-DECODE ERROR HANDLING VIA BRANCH CORRECTION 审中-公开
标题翻译：通过分支纠正预解码错误处理
公开(公告)号：WO2006057907A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/041850
申请日：2005-11-18
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney Wayne , STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as "mispredicted not taken" with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在流水线处理器中，指令在被存储在高速缓存中之前被预解码，在流水线中执行期间检测到不正确的预解码指令。相应的指令在高速缓存中失效，并且该指令被强制评估为分支指令。特别地，分支指令被评估为“未预测到错误预测” 与不正确的预解码指令地址的分支目标地址。这与无效的高速缓存行一起导致不正确的预解码指令从具有精确地址的存储器重新获取。重新获取的指令然后被正确地预解码，写入缓存并执行。

2. 发明申请

WO2006096568A2 POWER SAVING METHODS AND APPARATUS TO SELECTIVELY ENABLE CACHE BITS BASED ON KNOWN PROCESSOR STATE 审中-公开
标题翻译：基于已知处理器状态的省电方法和选择性使能的缓存器的设备
公开(公告)号：WO2006096568A2
公开(公告)日：2006-09-14
申请号：PCT/US2006/007758
申请日：2006-03-03
申请人： QUALCOMM Incorporated , STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SMITH, Rodney Wayne , SARTORIUS, Thomas Andrew
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SMITH, Rodney Wayne , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

3. 发明申请

WO2006060198A1 TRANSLATION LOOKASIDE BUFFER (TLB) SUPPRESSION FOR INTRA-PAGE PROGRAM COUNTER RELATIVE OR ABSOLUTE ADDRESS BRANCH INSTRUCTIONS 审中-公开
标题翻译：翻译LOOKASIDE BUFFER（TLB）抑制内部程序计数器相对或绝对地址分配指令
公开(公告)号：WO2006060198A1
公开(公告)日：2006-06-08
申请号：PCT/US2005/041998
申请日：2005-11-17
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne , STEMPEL, Brian Michael
发明人： DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： C07D209/42 , C07D493/08 , C07D405/12 , C07D403/12 , C07D401/12 , A61K31/404 , A61K31/435 , A61K31/4439 , A61K31/454 , A61K31/55
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对的分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA在同一个页面中，如BTSP位所指示的那样，则抑制对BTA的许可属性的TLB访问被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

4. 发明申请

WO2008055045A1 A SYSTEM AND METHOD FOR USING A WORKING GLOBAL HISTORY REGISTER 审中-公开
标题翻译：一种使用工作全球历史寄存器的系统和方法
公开(公告)号：WO2008055045A1
公开(公告)日：2008-05-08
申请号：PCT/US2007/082538
申请日：2007-10-25
申请人： QUALCOMM INCORPORATED , STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3804 , G06F9/3806 , G06F9/3861
摘要： A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register, wherein the first register. The method further loads the branch history information into the second register during the second pipeline stage.
摘要翻译：公开了处理分支历史信息的方法。该方法从指令高速缓存中检索分支指令，并在多个流水线级中执行分支指令。该方法验证分支指令已被识别。该方法还在第一流水线阶段期间接收分支历史信息，并将分支历史信息加载到第一寄存器中，其中第一寄存器。该方法在第二流水线阶段期间进一步将分支历史信息加载到第二寄存器中。

5. 发明申请

WO2007143508A2 SLIDING-WINDOW, BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：滑动窗口，基于块的分支目标地址高速缓存
公开(公告)号：WO2007143508A2
公开(公告)日：2007-12-13
申请号：PCT/US2007/070111
申请日：2007-05-31
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3844
摘要： A sliding-window, block-based branch target address cache (BTAC) comprises a plurality of entries, each entry associated with a block of instructions containing at least one branch instruction having been evaluated taken, and having a tag associated with the address of the first instruction in the block. The blocks each correspond to a group of instructions fetched from memory, such as an I-cache. Where a branch instruction is included in two or more fetch groups, it is also included in two or more instruction blocks associated with BTAC entries. The sliding-window, block-based BTAC allows for storing the branch target address (BTA) of two or more taken branch instructions that fall in the same instruction block, without providing for multiple BTA storage space in each BTAC entry, by storing BTAC entries associated with different instruction blocks, each containing at least one of the taken branch instructions.
摘要翻译：滑动窗口，基于块的分支目标地址高速缓存（BTAC）包括多个条目，每个条目与包含已被评估的至少一个分支指令的指令块相关联，并且具有与该地址相关联的标签第一个指令在块中。这些块各自对应于从存储器获取的一组指令，例如I缓存。在两个或更多个取出组中包含分支指令的情况下，还包括在与BTAC条目相关联的两个或多个指令块中。滑动窗口，基于块的BTAC允许存储落在相同指令块中的两个或更多个采取的分支指令的分支目标地址（BTA），而不需要在每个BTAC条目中提供多个BTA存储空间，通过存储BTAC条目与不同的指令块相关联，每个指令块包含至少一个采取的分支指令。

6. 发明申请

WO2009046326A1 LINK STACK REPAIR OF ERRONEOUS SPECULATIVE UPDATE 审中-公开
标题翻译：链路堆栈修复错误的参数更新
公开(公告)号：WO2009046326A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/078789
申请日：2008-10-03
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
发明人： DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。一个差异表示在错误预测的分支指令之后推测发出链路堆栈写入指令，并将链路地址推送到链路堆栈上。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

7. 发明申请

WO2007101214A1 METHOD AND APPARATUS FOR REPAIRING A LINK STACK 审中-公开
标题翻译：修复链接堆栈的方法和装置
公开(公告)号：WO2007101214A1
公开(公告)日：2007-09-07
申请号：PCT/US2007/062904
申请日：2007-02-27
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James Norris , MANDZAK, David John , SMITH, Rodney Wayne , STEMPEL, Brian Michael
发明人： DIEFFENDERFER, James Norris , MANDZAK, David John , SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30054 , G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A link stack in a processor is repaired in response to a procedure return address misprediction error. In one example, a link stack for use in a processor is repaired by detecting an error in a procedure return address value retrieved from the link stack and skipping a procedure return address value currently queued for retrieval from the link stack responsive to detecting the error. In one or more embodiments, a link stack circuit comprises a link stack and a link stack pointer. The link stack is configured to store a plurality of procedure return address values. The link stack pointer is configured to skip a procedure return address value currently queued for retrieval from the link stack responsive to an error detected in a procedure return address value previously retrieved from the link stack.
摘要翻译：响应于过程返回地址错误预测错误，处理器中的链路堆栈被修复。在一个示例中，通过检测从链接堆栈检索到的过程返回地址值中的错误来修复处理器中使用的链接栈，并且响应于检测到错误，跳过当前排队等待从链接堆栈检索的过程返回地址值。在一个或多个实施例中，链路栈电路包括链路栈和链路栈指针。链路栈被配置为存储多个过程返回地址值。链路堆栈指针被配置为响应于先前从链路栈检索的过程返回地址值中检测到的错误，跳过当前排队等待从链路栈检索的过程返回地址值。

8. 发明申请

WO2013026055A1 LINK STACK REPAIR OF ERRONEOUS SPECULATIVE UPDATE 审中-公开
标题翻译：链路堆栈修复错误的参数更新
公开(公告)号：WO2013026055A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051578
申请日：2012-08-20
申请人： QUALCOMM INCORPORATED , DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
发明人： DIEFFENDERFER, James Norris , STEMPEL, Brian Michael , SMITH, Rodney Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

9. 发明申请

WO2008113007A1 SYSTEM, METHOD AND SOFTWARE TO PRELOAD INSTRUCTIONS FROM AN INSTRUCTION SET OTHER THAN ONE CURRENTLY EXECUTING 审中-公开
标题翻译：系统，方法和软件从除当前执行以外的指令集中提出指示
公开(公告)号：WO2008113007A1
公开(公告)日：2008-09-18
申请号：PCT/US2008/057064
申请日：2008-03-14
申请人： QUALCOMM Incorporated , SARTORIUS, Thomas Andrew , STEMPEL, Brian Michael , SMITH, Rodney Wayne
发明人： SARTORIUS, Thomas Andrew , STEMPEL, Brian Michael , SMITH, Rodney Wayne
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.
摘要翻译：在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

10. 发明申请

WO2007130798A1 PRE-DECODING VARIABLE LENGTH INSTRUCTIONS 审中-公开
标题翻译：预编译可变长度指令
公开(公告)号：WO2007130798A1
公开(公告)日：2007-11-15
申请号：PCT/US2007/067057
申请日：2007-04-20
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , STEMPEL, Brian Michael
发明人： SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30149 , G06F9/30152 , G06F9/30185 , G06F9/30192 , G06F9/3802 , G06F9/382
摘要： A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.
摘要翻译：可变指令长度处理器中的预解码器指示存储在具有指令的指令高速缓存中的预解码位中的指令的特性。当预解码位的所有编码与一个长度指令相关联时，可以通过改变指令来模拟不同长度的指令来指示该长度的指令的属性，并且在预解码中编码该属性与不同长度的指令相关联的位。可能如此指示的属性的一个示例是未定义的指令。

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