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41. 发明授权

US07817457B2 Non-volatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07817457B2
公开(公告)日：2010-10-19
申请号：US12132972
申请日：2008-06-04
申请人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
发明人： Naoya Tokiwa , Kazushige Kanda , Toshiaki Edahiro , Koji Hosono , Takuya Futatsuyama , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0097 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.
摘要翻译：根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

42. 发明申请

US20100034025A1 NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM 有权
标题翻译：非挥发性半导体存储系统
公开(公告)号：US20100034025A1
公开(公告)日：2010-02-11
申请号：US12507366
申请日：2009-07-22
申请人： Kosuke YANAGIDAIRA , Toshihiro Suzuki , Naoya Tokiwa
发明人： Kosuke YANAGIDAIRA , Toshihiro Suzuki , Naoya Tokiwa
IPC分类号： G11C16/04 , G11C7/00 , G11C29/00
CPC分类号： G11C16/349
摘要： There is provided a non-volatile memory having electrically rewritable non-volatile memory cells arranged therein. A controller controls operation at the non-volatile memory. The non-volatile memory comprises a status output section configured to output status information indicating a status of read operation, write operation or erase operation in the non-volatile memory cell. The controller comprises a control signal generating section configured to output a control signal for a certain operation in the non-volatile memory, and a control signal switching section configured to instruct the control signal generating section to switch the control signal based on the status information.
摘要翻译：提供了一种其中布置有电可重写非易失性存储单元的非易失性存储器。控制器控制非易失性存储器的操作。非易失性存储器包括状态输出部分，被配置为在非易失性存储器单元中输出指示读取操作，写入操作或擦除操作的状态的状态信息。所述控制器包括：控制信号生成部，被配置为输出用于所述非易失性存储器中的某个操作的控制信号;以及控制信号切换部，被配置为指示所述控制信号生成部基于所述状态信息来切换所述控制信号。

43. 发明申请

US20090154237A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090154237A1
公开(公告)日：2009-06-18
申请号：US12277698
申请日：2008-11-25
申请人： Naoya TOKIWA
发明人： Naoya TOKIWA
IPC分类号： G11C16/00 , G11C16/06 , G11C16/04 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C16/20
摘要： A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area.
摘要翻译：非易失性半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 配置为存储用于控制存储器操作的控制数据的第一寄存器组; 在所述存储单元阵列中定义的调整数据存储区域，以存储用于调整所述控制数据的调整数据; 以及第二寄存器组，被配置为存储从调整数据存储区域读取的调整数据。

44. 发明申请

US20090109728A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090109728A1
公开(公告)日：2009-04-30
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 DeltaR2的关系。

45. 发明申请

US20090052227A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20090052227A1
公开(公告)日：2009-02-26
申请号：US12118064
申请日：2008-05-09
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

46. 发明申请

US20080170435A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20080170435A1
公开(公告)日：2008-07-17
申请号：US12015755
申请日：2008-01-17
申请人： Naoya Tokiwa , Norihiro Fujita
发明人： Naoya Tokiwa , Norihiro Fujita
IPC分类号： G11C16/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.
摘要翻译：存储单元阵列具有布置在其中的多个多值存储器单元，其可以将一个存储单元中的两位或更多位的信息存储为不同的页。在每个数据寄存器中，临时保存从存储单元阵列读取的数据的可接受数量设置寄存器存储与多值存储器单元中的每个页的阈值电压的每种状态相对应的多个可接受数量的数据状态。选择器从多个可接受数量的数据状态中选择对应于多值存储器单元的每一页的每个数据寄存器中保留的数据的可接受数量的数据状态。比较器将每个数据寄存器中保留的数据状态数与选择器选择的可接受的数据状态数进行比较。

47. 发明申请

US20080123410A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20080123410A1
公开(公告)日：2008-05-29
申请号：US11773280
申请日：2007-07-03
申请人： Masanobu Shirakawa , Naoya Tokiwa
发明人： Masanobu Shirakawa , Naoya Tokiwa
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C29/835
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 行解码器，其被配置为选择存储单元阵列中的存储单元，所述行解码器包括标志锁存器，其中对所述存储单元阵列中的坏块设置坏块标志; 感测放大器，被配置为感测所述存储器单元阵列中的选定存储单元的数据; 以及输出电路，被配置为在所述读出放大器中输出读取数据，所述输出电路包括输出数据固定电路，其被配置为根据所述坏块标志将输出数据固定在逻辑电平。

48. 发明授权

US06950345B1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06950345B1
公开(公告)日：2005-09-27
申请号：US10874361
申请日：2004-06-24
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/22
摘要： A nonvolatile semiconductor memory device with a function of executing a verify operation for write data that is input from outside includes a memory cell array including memory cells arranged in a matrix, and a password storage area for storing password data, an input buffer that receives data input from outside, a first retaining circuit that retains input password data or write data, which is input to the input buffer, a verify sense amplifier that detects, at a time of the verify operation, the password data that is read out of the password storage area or data that is read out of the memory cell array, and a coincidence determination circuit that determines whether the input password data coincides with the read-out password data, or determines whether the write data coincides with the read-out data.
摘要翻译：具有执行从外部输入的写入数据的验证操作的功能的非易失性半导体存储器件包括：存储单元阵列，包括以矩阵形式排列的存储单元;以及用于存储密码数据的密码存储区域;接收数据的输入缓冲器来自外部的输入，保持输入到输入缓冲器的输入密码数据或写入数据的第一保持电路，在验证操作时检测从密码读出的密码数据的验证读出放大器存储区域或从存储单元阵列读出的数据，以及一致确定电路，其确定输入的密码数据是否与读出的密码数据一致，或者确定写入数据是否与读出的数据一致。

49. 发明申请

US20110249498A1 THREE-DIMENSIONALLY STACKED NONVOLATILE SEMICONDUTOR MEMORY 有权
标题翻译：三维堆叠非易失性半导体存储器
公开(公告)号：US20110249498A1
公开(公告)日：2011-10-13
申请号：US13164938
申请日：2011-06-21
申请人： Naoya TOKIWA , Hideo Mukai
发明人： Naoya TOKIWA , Hideo Mukai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08 , G11C16/30 , G11C29/028 , G11C2029/1202 , H01L27/11578 , H01L27/11582
摘要： A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.
摘要翻译：本发明的一个方面的三维叠层的非易失性半导体存储器包括以彼此绝缘的方式堆叠在半导体衬底上的导电层，布置在层叠的导电层上的位线，半导体柱其延伸穿过堆叠的导电层，使用除了最上面和最下面的导电层之外的层叠的导电层并且具有板状平面形状的字线，设置在字线和半导体柱的交叉处的存储单元，具有提供适于每个字线的电位的信息的寄存器电路以及根据字线的输入地址信号读取保存在寄存器电路中的信息的电位控制电路，并提供适于对应于地址信号的字线。

50. 发明授权

US08000155B2 Non-volatile memory device and method for writing data thereto 有权
公开(公告)号：US08000155B2
公开(公告)日：2011-08-16
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C7/22 , G11C7/06 , G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

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