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41. 发明申请

US20060268592A1 Low power microprocessor cache memory and method of operation 有权
公开(公告)号：US20060268592A1
公开(公告)日：2006-11-30
申请号：US11137183
申请日：2005-05-25
申请人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
发明人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
IPC分类号： G11C15/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.

42. 发明申请

US20060230259A1 Instruction memory unit and method of operation 有权
标题翻译：指令存储单元和操作方法
公开(公告)号：US20060230259A1
公开(公告)日：2006-10-12
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William Anderson , Robert Lester , Phillip Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William Anderson , Robert Lester , Phillip Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译：指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从如果目标指令没有存储在第二存储器结构中的第一存储器结构。

43. 发明申请

US20060224862A1 Mixed superscalar and VLIW instruction issuing and processing method and system 有权
公开(公告)号：US20060224862A1
公开(公告)日：2006-10-05
申请号：US11093375
申请日：2005-03-29
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.

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