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41. 发明授权

US07696046B2 Method of manufacturing a semiconductor device having a multi-channel type MOS transistor 有权
标题翻译：制造具有多通道型MOS晶体管的半导体器件的方法
公开(公告)号：US07696046B2
公开(公告)日：2010-04-13
申请号：US11876613
申请日：2007-10-22
申请人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
发明人： Min-Sang Kim , Sung-Young Lee , Sung-Min Kim , Eun-Jung Yun , In-Hyuk Choi
IPC分类号： H01L21/336 , H01L21/20 , H01L21/31 , H01L21/469
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.
摘要翻译：在制造半导体器件的方法中，在衬底上形成有源沟道图案。有源沟道图案包括彼此交替堆叠的初步栅极图案和单晶硅图案。源极/漏极层形成在有源沟道图案的侧壁上。在有源沟道图案和源极/漏极层上形成包括栅极沟槽的掩模图案结构。选择性地蚀刻图案以形成隧道。然后用栅电极填充栅极沟槽。栅电极围绕有源沟道图案。栅电极从有源沟道图案突出。然后去除掩模图案结构。将杂质注入源/漏区以形成源/漏区。在源极/漏极区域上进行硅化处理以形成金属硅化物层，从而完成具有MOS晶体管的半导体器件。

42. 发明申请

US20100088154A1 SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR COMPUTING AND OUTPUTTING A TIMELINE VALUE, INDICATION OF POPULARITY, AND RECOMMENDATION 审中-公开
标题翻译：用于计算和输出时间表价值的指标体系，方法和计算机程序产品及其建议
公开(公告)号：US20100088154A1
公开(公告)日：2010-04-08
申请号：US12569668
申请日：2009-09-29
申请人： Aditya Vailaya , Jiang Wu , Robert Lincoln Lewis, JR. , Vipin Jain , Manish Rathi , Min Sang Kim , Jeffrey Ronne
发明人： Aditya Vailaya , Jiang Wu , Robert Lincoln Lewis, JR. , Vipin Jain , Manish Rathi , Min Sang Kim , Jeffrey Ronne
IPC分类号： G06Q10/00 , G06Q30/00 , G06N5/02
CPC分类号： G06Q30/02 , G06Q10/04 , G06Q30/0201 , G06Q30/0251
摘要： A computer-implemented method is provided for computing and outputting a timeline value. In use, model data about a product is received. Additionally, thresholds relevant to the model data are received or computed. Further, a timeline value is computed based on comparing the thresholds to the model data, where the timeline value is indicative of a current stage in a lifecycle of the product. Further still, the timeline value is output. Additional systems, methods and computer program products are also implemented. For example, methods are presented for computing and outputting an indication of product buzz and/or popularity. Other methods include using one or more of timeline, popularity, sentiment, value, discount ratings, etc. to compute a recommendation and output the same.
摘要翻译：提供了一种用于计算和输出时间轴值的计算机实现的方法。在使用中，收到有关产品的模型数据。另外，接收或计算与模型数据相关的阈值。此外，基于将阈值与模型数据进行比较来计算时间线值，其中时间线值表示产品的生命周期中的当前阶段。此外，输出时间轴值。还实现了其他系统，方法和计算机程序产品。例如，提出了用于计算和输出产品蜂声和/或流行性的指示的方法。其他方法包括使用时间轴，流行度，情绪，价值，折扣等等中的一个或多个来计算推荐并输出相同的方法。

43. 发明申请

US20100059807A1 Semiconductor device having bar type active pattern 有权
标题翻译：具有棒式有源图案的半导体器件
公开(公告)号：US20100059807A1
公开(公告)日：2010-03-11
申请号：US12461500
申请日：2009-08-13
申请人： Keun-hwl Cho , Dong-won Kim , Jun Seo , Min-sang Kim , Sung-min Kim , Hyun-jun Bae , Ji-Myoung Lee
发明人： Keun-hwl Cho , Dong-won Kim , Jun Seo , Min-sang Kim , Sung-min Kim , Hyun-jun Bae , Ji-Myoung Lee
IPC分类号： H01L27/108
CPC分类号： H01L29/66795 , H01L27/10814 , H01L27/10873 , H01L27/10879 , H01L29/785
摘要： A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.
摘要翻译：提供了具有条形有源图案的半导体器件及其制造方法。半导体器件可以包括具有半导体鳍片的半导体衬底，半导体鳍片被配置为在第一方向上从半导体衬底的表面突出，半导体衬底具有与第一宽度交叉的第一宽度和第二宽度，其中第一宽度和第二宽度宽度在第二方向上延伸。多个有源图案可以在第一方向上与半导体鳍片分离间隙布置。多个支撑图案可以布置在半导体翅片与沿着第一方向布置得更靠近半导体鳍片的多个有源图案中的一个之间以及沿着第一方向布置的多个有源图案之间，以支撑多个有源图案。栅极可以布置成在第二方向上跨越多个有源图案并且覆盖多个有源图案中的至少一个的一部分。

44. 发明申请

US20090115009A1 Multibit electro-mechanical memory device and manufacturing method thereof 有权
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US20090115009A1
公开(公告)日：2009-05-07
申请号：US12289851
申请日：2008-11-06
申请人： Ji-Myoung Lee , Min-Sang Kim , Sung-Min Kim , Keun-Hwl Cho
发明人： Ji-Myoung Lee , Min-Sang Kim , Sung-Min Kim , Keun-Hwl Cho
IPC分类号： H01L29/66 , H01L21/00
CPC分类号： G11C11/56 , B82Y10/00 , G11C13/025 , G11C23/00
摘要： Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions.
摘要翻译：提供了一种多位机电存储器件及其制造方法。器件可以在衬底上包括沿第一方向的至少一个位线; 至少一个栅极线和至少一个下部字线平行延伸给定的间隔，并且在与所述至少一个位线上的所述第一方向相交的第二方向上; 至少一个与所述至少一条位线上的所述至少一条栅极线相邻的接触焊盘; 以及耦合到所述至少一个接触垫的至少一个悬臂电极，其构造成在所述至少一个悬臂电极的上方和下方浮动，并且被配置为在垂直于所述第一和第二方向的第三方向上弯曲。

45. 发明申请

US20090097315A1 Multibit electro-mechanical memory device and method of manufacturing the same 失效
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US20090097315A1
公开(公告)日：2009-04-16
申请号：US12154473
申请日：2008-05-23
申请人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
发明人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Sung-Young Lee , Ji-Myoung Lee , In-Hyuk Choi
IPC分类号： G11C16/00 , H01L27/00 , H01L21/00
CPC分类号： H01L27/10 , G11C11/50 , H01L27/115
摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.
摘要翻译：多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线网站。

46. 发明授权

US07511998B2 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07511998B2
公开(公告)日：2009-03-31
申请号：US11803425
申请日：2007-05-15
申请人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Dong-Gun Park , Eun-Jung Yun
发明人： Sung-Young Lee , Dong-Won Kim , Min-Sang Kim , Dong-Gun Park , Eun-Jung Yun
IPC分类号： G11C16/04
CPC分类号： H01L27/101 , H01L27/24
摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.
摘要翻译：非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

47. 发明申请

US20080093686A1 ELECTROMECHANICAL NON-VOLATILE MEMORY DEVICES 失效
标题翻译：电子非易失性存储器件
公开(公告)号：US20080093686A1
公开(公告)日：2008-04-24
申请号：US11876111
申请日：2007-10-22
申请人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Sung-Young Lee , Min-Sang Kim , Sung-Min Kim
IPC分类号： H01L45/00
CPC分类号： H01L27/10 , G11C23/00
摘要： Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern.
摘要翻译：提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。第一电极图案设置在半导体衬底上。第一电极图案暴露半导体衬底的表面的部分通过其中。在第一电极图案和半导体衬底的暴露表面上提供保形位线。位线与第一电极图案的侧壁间隔开，并且包括具有由电压差产生的弹性的导电材料。绝缘层图案设置在位于半导体衬底上的位线的上表面上。第二电极图案与位线间隔开并设置在绝缘层图案上。第二电极图案面向第一电极图案。

48. 发明申请

US20060192249A1 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 审中-公开
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US20060192249A1
公开(公告)日：2006-08-31
申请号：US11396488
申请日：2006-04-03
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

49. 发明申请

US20050269629A1 Fin field effect transistors and methods of fabricating the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US20050269629A1
公开(公告)日：2005-12-08
申请号：US11084922
申请日：2005-03-21
申请人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
发明人： Chul Lee , Min-Sang Kim , Dong-gun Park , Choong-ho Lee , Chang-woo Oh , Jae-man Yoon , Dong-won Kim , Jeong-dong Choe , Ming Li , Hye-jin Cho
IPC分类号： H01L21/00 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/84 , H01L29/76 , H01L29/786 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L21/26513 , H01L21/845 , H01L29/66795 , H01L29/78624
摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.
摘要翻译：翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。翅片在基底上并沿着和垂直方向横向延伸。栅电极覆盖翅片的一侧和顶部。栅绝缘层位于栅电极和鳍之间。翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。翅片的源极区域具有与鳍片的漏极区域不同的宽度。

50. 发明授权

US08858011B2 Backlight unit and display apparatus using the same 有权
标题翻译：背光单元和使用其的显示装置
公开(公告)号：US08858011B2
公开(公告)日：2014-10-14
申请号：US13368673
申请日：2012-02-08
申请人： Min Sang Kim , Jung In Seo
发明人： Min Sang Kim , Jung In Seo
IPC分类号： G09F13/04 , F21V8/00
CPC分类号： G02B6/0021 , G02B6/0038 , G02B6/0055 , G02B6/0068 , G02B6/0073
摘要： The backlight unit includes a plurality of light source groups, each of which includes at least one light source, and a light guide plate to guide light irradiated from the plurality of light source groups, and the light guide plate includes first grooves disposed in a first direction, the plurality of light source groups being disposed within the first grooves, and at least one second groove disposed in a second direction differing from the first direction.
摘要翻译：背光单元包括多个光源组，每个光源组包括至少一个光源，以及导光板，用于引导从多个光源组照射的光，并且导光板包括设置在第一所述多个光源组设置在所述第一凹槽内，以及至少一个第二凹槽，所述第二凹槽沿与第一方向不同的第二方向设置。

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