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41. 发明申请

US20070050592A1 Method and apparatus for accessing misaligned data streams 审中-公开
标题翻译：访问未对齐数据流的方法和装置
公开(公告)号：US20070050592A1
公开(公告)日：2007-03-01
申请号：US11216659
申请日：2005-08-31
申请人： Michael Gschwind , John Wellman
发明人： Michael Gschwind , John Wellman
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0886 , G06F9/30036 , G06F9/3816 , G06F9/3824 , G06F9/383 , G06F12/04 , G06F12/0831
摘要： One embodiment of the present method and apparatus for accessing misaligned data streams includes receiving a data request, where the data request includes a request for misaligned data, and retrieving at least a portion of the requested data from a data stream buffer associated with the data stream. If the data retrieved from the data stream buffer does not comprise all of the requested data, the remainder of the requested data is retrieved from memory and combined with the data stream buffer data. In this manner, the number of memory accesses necessary to retrieve the requested misaligned data is reduced. Additional embodiments of the present invention include mechanisms for ensuring data coherence with respect to write updates and protocol requests. Moreover, the present invention advantageously reduces the need for pipeline upset events/pipeline hazards that typically result in performance degradation in pipelined microprocessors.
摘要翻译：用于访问不对准数据流的本方法和装置的一个实施例包括接收数据请求，其中数据请求包括对未对准数据的请求，以及从与数据流相关联的数据流缓冲器中检索所请求的数据的至少一部分。如果从数据流缓冲器检索的数据不包括所有请求的数据，则从存储器检索所请求数据的剩余部分并与数据流缓冲器数据组合。以这种方式，减少了检索所请求的不对准数据所需的存储器访问的数量。本发明的另外的实施例包括用于确保关于写入更新和协议请求的数据一致性的机制。此外，本发明有利地减少了管道不安事件/管道危害的需要，这通常导致流水线微处理器的性能下降。

42. 发明申请

US20070038984A1 Methods for generating code for an architecture encoding an extended register specification 审中-公开
标题翻译：用于为编码扩展寄存器规范的体系结构生成代码的方法
公开(公告)号：US20070038984A1
公开(公告)日：2007-02-15
申请号：US11446031
申请日：2006-06-02
申请人： Michael Gschwind , Robert Montoye , Brett Olsson , John-David Wellman
发明人： Michael Gschwind , Robert Montoye , Brett Olsson , John-David Wellman
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.
摘要翻译：提供了用于为编码扩展寄存器规范的架构生成代码的方法和计算机程序产品。用于生成固定宽度指令集的代码的方法包括识别不连续的寄存器说明符。该方法还包括生成包括非连续寄存器说明符的固定宽度指令字。

43. 发明申请

US20060155965A1 Method and apparatus for control signals memoization in a multiple instruction issue microprocessor 失效
标题翻译：用于在多指令发出微处理器中控制信号记忆的方法和装置
公开(公告)号：US20060155965A1
公开(公告)日：2006-07-13
申请号：US11034284
申请日：2005-01-12
申请人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
发明人： Erik Altman , Michael Gschwind , Jude Rivers , Sumedh Sathaye , John-David Wellman , Victor Zyuban
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/3838 , G06F9/3859 , G06F9/3873
摘要： A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.
摘要翻译：在微处理器管线的各个阶段提供动态预测和/或精确缓存机制，使得可以在程序执行过程中存储和存储各种控制信号。精确的控制信号矢量缓存可以完成。每当在指令解码，注册重命名和依赖关系检查之后形成问题组时，可以在引导指令的标签下缓存问题组信息的编码副本。所产生的依赖性高速缓存或控制向量高速缓存可以在微处理器流水线的指令发出逻辑阶段的开始时被下一次相应的指令组出现以重新执行。由于可以在高速缓存中的单个周期中访问编码的问题组位模式，所以具有该实施例的所得微处理器流水线可以被看作是两个并行的管道，其中如果存在依赖性高速缓存或控制向量高速缓存击中。

44. 发明授权

US06907477B2 Symmetric multi-processing system utilizing a DMAC to allow address translation for attached processors 失效
标题翻译：使用DMAC的对称多处理系统允许连接的处理器进行地址转换
公开(公告)号：US06907477B2
公开(公告)日：2005-06-14
申请号：US10782044
申请日：2004-02-19
申请人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/28 , G06F9/28 , G06F13/368
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMT system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：一种用于附接处理单元访问SMT系统中的共享存储器的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

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