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41. 发明授权

US5747853A Semiconductor structure with controlled breakdown protection 失效
标题翻译：具有受控击穿保护的半导体结构
公开(公告)号：US5747853A
公开(公告)日：1998-05-05
申请号：US693950
申请日：1996-08-07
申请人： Koon Chong So , Fwu-Iuan Hshieh , Danny C. Nim , True-Lon Line , Yan Man Ysui
发明人： Koon Chong So , Fwu-Iuan Hshieh , Danny C. Nim , True-Lon Line , Yan Man Ysui
IPC分类号： H01L29/06 , H01L29/78 , H01L23/62
CPC分类号： H01L29/0626 , H01L29/7802 , H01L2924/0002
摘要： A power semiconductor device having internal circuits characterized by an electrical breakdown during one mode of operation is implemented with a protective circuit. The electrical breakdown is controllably induced to occur at the protective circuit thereby diverting any breakdown in the active circuits. In the preferred embodiment, the power device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in which the protective circuit is deposited as an annular diffusion ring having a shallow portion and a deep portion. The deep portion is higher in doping concentration than the shallow portion and includes a radius of curvature larger than the shallow portion. The radius of curvature of the deep portion can be adjusted to induce breakdown at or above the rated value of the MOSFET. The predetermined doping concentration of the deep portion can abort the breakdown prematurely to occur at the deep region instead of at the active circuits. Electrical contacts are tied to the annular diffusion ring to gravitate any charge carriers generated during the electrical breakdown so as to prevent the charge carriers from reaching the active circuits, thereby further ensuing no breakdown at the internal circuits.
摘要翻译：具有在一种操作模式下由电击穿特征的内部电路的功率半导体器件用保护电路实现。电击穿可控制地发生在保护电路处，从而转移有源电路中的任何击穿。在优选实施例中，功率器件是其中保护电路作为具有浅部分和深部的环形扩散环沉积的MOSFET（金属氧化物半导体场效应晶体管）。深部分的掺杂浓度高于浅部，并且包括大于浅部的曲率半径。可以调整深部的曲率半径，以便在MOSFET的额定值以上引起击穿。深部分的预定掺杂浓度可以过早地中止击穿在深部区域而不是在有源电路处发生。电触点被连接到环形扩散环以引起在电击穿期间产生的任何电荷载体，以防止电荷载流子到达有源电路，从而进一步导致内部电路没有击穿。

42. 发明申请

US20090233415A1 Semiconductor Devices with Sealed, Unlined Trenches and Methods of Forming Same 有权
标题翻译：具有密封，无衬底的沟槽的半导体器件及其形成方法
公开(公告)号：US20090233415A1
公开(公告)日：2009-09-17
申请号：US12472424
申请日：2009-05-27
申请人： Samuel Anderson , Koon Chong So
发明人： Samuel Anderson , Koon Chong So
IPC分类号： H01L21/764
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/872
摘要： A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
摘要翻译：半导体器件包括无衬里和密封的沟槽以及用于形成无衬里和密封沟槽的方法。更具体地说，超结半导体器件包括无衬里和密封的沟槽。沟槽具有由半导体材料形成的侧壁。沟槽用密封材料密封，使得沟槽是气密的。第一和第二区域被沟槽分开。第一区域可以包括超连接肖特基二极管或MOSFET。在替代实施例中，多个区域被多个无衬里和密封的沟槽隔开。

43. 发明授权

US06977203B2 Method of forming narrow trenches in semiconductor substrates 有权
标题翻译：在半导体衬底中形成窄沟槽的方法
公开(公告)号：US06977203B2
公开(公告)日：2005-12-20
申请号：US10010162
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Brian D. Pratt
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/308 , H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/12 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/311 , H01L21/3205
CPC分类号： H01L21/3088 , H01L21/3086
摘要： A method of forming a trench within a semiconductor substrate. The method comprises, for example, the following: (a) providing a semiconductor substrate; (b) providing a patterned first CVD-deposited masking material layer having a first aperture over the semiconductor substrate; (c) depositing a second CVD-deposited masking material layer over the first masking material layer; (d) etching the second masking material layer until a second aperture that is narrower than the first aperture is created in the second masking material within the first aperture; and (e) etching the semiconductor substrate through the second aperture such that a trench is formed in the semiconductor substrate. In preferred embodiments, the method of the present invention is used in the formation of trench MOSFET devices.
摘要翻译：一种在半导体衬底内形成沟槽的方法。该方法例如包括以下：（a）提供半导体衬底; （b）提供在半导体衬底上具有第一孔的图案化的第一CVD沉积掩模材料层; （c）在所述第一掩蔽材料层上沉积第二CVD沉积的掩模材料层; （d）蚀刻所述第二掩模材料层，直到在所述第一孔径内的所述第二掩模材料中产生比所述第一孔径窄的第二孔径; 以及（e）通过所述第二孔蚀刻所述半导体衬底，使得在所述半导体衬底中形成沟槽。在优选实施例中，本发明的方法用于形成沟槽MOSFET器件。

44. 发明授权

US06822288B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
标题翻译：沟槽MOSFET器件，具有多晶硅源接触结构
公开(公告)号：US06822288B2
公开(公告)日：2004-11-23
申请号：US10010484
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.
摘要翻译：沟槽MOSFET晶体管器件及其制造方法。该装置包括：（a）第一导电类型的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）第二导电类型的体区，设置在所述外延层的上部并且与所述沟槽相邻; （g）第一导电类型的源极区域，设置在所述主体区域的上部并且邻近所述沟槽; （h）第二导电类型的上部区域，在所述主体区域的上部并且邻近所述源极区域，所述上部区域具有比所述身体区域更高的载流子浓度; 和（i）设置在所述外延层上表面上的源极接触区域，其中所述源极接触区域包括与所述源极区域电接触的掺杂多晶硅接触区域以及与所述源极区域电接触的相邻金属接触区域和上部区域。

45. 发明授权

US06781196B2 Trench DMOS transistor having improved trench structure 失效
标题翻译：具有改善沟槽结构的沟槽DMOS晶体管
公开(公告)号：US06781196B2
公开(公告)日：2004-08-24
申请号：US10094932
申请日：2002-03-11
申请人： Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
发明人： Koon Chong So , Fwu-Iuan Hshieh , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4238 , H01L29/7811
摘要： A trench DMOS transistor cell is provided that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.
摘要翻译：提供了沟槽DMOS晶体管单元，其包括第一导电类型的衬底和位于衬底上的具有第二导电类型的体区。至少一个沟槽延伸穿过身体区域和衬底。绝缘层对沟槽进行排列，并且将导电电极放置在覆盖绝缘层的沟槽中。第一导电类型的源极区位于与沟槽相邻的体区中。沟槽具有在衬底的平面中限定多边形的侧壁，使得相邻的侧壁以大于90度的角度彼此接触。

46. 发明授权

US06713352B2 Method of forming a trench MOSFET with structure having increased cell density and low gate charge 失效
标题翻译：形成具有增加的电池密度和低栅极电荷的结构的沟槽MOSFET的方法
公开(公告)号：US06713352B2
公开(公告)日：2004-03-30
申请号：US10243849
申请日：2002-09-13
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/4238 , H01L2924/0002 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.
摘要翻译：沟槽MOSFET包括在外延层的上表面中的多个沟槽段，其延伸穿过第二导电类型区域到第一导电类型外延区域，至少部分地通过端接区域与相邻区段部分地分离，并且沟槽段限定第二导电类型内的多个多边形体区域。至少部分地对每个沟槽进行排列的第一绝缘层和多个第一导电区域设置在与第一层相邻的沟槽段内。每个导电区域通过覆盖终止区域的连接导电区域连接到相邻的第一导电区域，桥接至少一个端接区域和多个第一导电类型源极区域在多边形体的上部区域并且与沟槽区段相邻，源区域位于终止区域的外部。

47. 发明授权

US06707127B1 Trench schottky rectifier 有权
标题翻译：沟槽肖特基整流器
公开(公告)号：US06707127B1
公开(公告)日：2004-03-16
申请号：US09653084
申请日：2000-08-31
申请人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
IPC分类号： H01L27095
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
摘要翻译：提供肖特基整流器。肖特基整流器包括：（a）具有第一和第二相对面的半导体区域，半导体区域包括邻近第一面的第一导电类型的阴极区域和与第二面相邻的第一导电类型的漂移区域，以及漂移区具有比阴极区更低的净掺杂浓度; （b）从所述第二面延伸到所述半导体区域并限定所述半导体区域内的一个或多个台面的一个或多个沟槽; （c）与沟槽下部的半导体区相邻的绝缘区; （d）和阳极电极（i）在第二面处与半导体相邻并形成肖特基整流接触，（ii）与沟槽上部的半导体区域相邻并形成肖特基整流接触，以及（iii）与沟槽下部的绝缘区域相邻。

48. 发明授权

US06630402B2 Integrated circuit resistant to the formation of cracks in a passivation layer 失效
标题翻译：集成电路可抵抗钝化层中裂纹的形成
公开(公告)号：US06630402B2
公开(公告)日：2003-10-07
申请号：US09990460
申请日：2001-11-21
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato
IPC分类号： H01L2100
CPC分类号： H01L21/76838 , H01L23/3171 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.
摘要翻译：在通过蚀刻和镶嵌技术制造的集成电路中，通常在集成到器件中的互连金属层周围的电介质材料中发生破裂，这可能是由于互连金属层到周围电介质材料的应力传递的结果。本发明通过提供一种互连金属层来解决这个问题，该互连金属层包括被认为能够减少传递到周围电介质层的应力的圆角。

49. 发明授权

US06620691B2 Semiconductor trench device with enhanced gate oxide integrity structure 有权
标题翻译：在沟槽中制造具有不同厚度的栅极氧化物层的沟槽dmos结构的方法
公开(公告)号：US06620691B2
公开(公告)日：2003-09-16
申请号：US10042558
申请日：2001-11-20
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.
摘要翻译：提供了一种用于制造沟槽DMOS的方法，其改善了具有设置在器件的有源区域中的至少第一沟槽的器件中的氧化物层的击穿电压以及设置在器件的端接区域中的第二沟槽。根据该方法，使用掩模技术使第二沟槽的顶角附近的氧化物层变厚，从而补偿由于两者而发生的该区域的薄化（以及伴随的击穿电压降低）在制造过程中的三维氧化。

50. 发明授权

US06593620B1 Trench DMOS transistor with embedded trench schottky rectifier 有权
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06593620B1
公开(公告)日：2003-07-15
申请号：US09684931
申请日：2000-10-06
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
IPC分类号： H01L27148
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/7806 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit includes: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (t) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.
摘要翻译：一种在一个或多个整流器区域内具有多个沟道肖特基势垒整流器的集成电路以及一个或多个晶体管区域内的多个沟槽DMOS晶体管。集成电路包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的掺杂水平; （c）晶体管区域中的外延层内的第二导电类型的多个体区; （d）在晶体管区域和整流器区域中的外延层内的多个沟槽; （e）对沟槽进行排列的第一绝缘层; （t）沟槽内的多晶硅导体，并覆盖第一绝缘层; （g）在与所述沟槽相邻的位置处的所述主体区域内的所述第一导电类型的多个源极区域; （h）晶体管区域上的掺杂多晶硅层上的第二绝缘层; 和（i）在晶体管区域和整流器区域上的电极层。

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