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1. 发明授权

US06518152B2 Method of forming a trench schottky rectifier 失效
标题翻译：形成沟槽肖特基整流器的方法
公开(公告)号：US06518152B2
公开(公告)日：2003-02-11
申请号：US10043633
申请日：2002-01-10
申请人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2128
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
摘要翻译：提供肖特基整流器。肖特基整流器包括：（a）具有第一和第二相对面的半导体区域，半导体区域包括邻近第一面的第一导电类型的阴极区域和与第二面相邻的第一导电类型的漂移区域，以及漂移区具有比阴极区更低的净掺杂浓度; （b）从所述第二面延伸到所述半导体区域并限定所述半导体区域内的一个或多个台面的一个或多个沟槽; （c）与沟槽下部的半导体区相邻的绝缘区; （d）和阳极电极（i）在第二面处与半导体相邻并形成肖特基整流接触，（ii）与沟槽上部的半导体区域相邻并形成肖特基整流接触，以及（iii）与沟槽下部的绝缘区域相邻。

2. 发明授权

US06707127B1 Trench schottky rectifier 有权
标题翻译：沟槽肖特基整流器
公开(公告)号：US06707127B1
公开(公告)日：2004-03-16
申请号：US09653084
申请日：2000-08-31
申请人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Max Chen , Koon Chong So , Yan Man Tsui
IPC分类号： H01L27095
CPC分类号： H01L29/8725 , H01L29/872
摘要： A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
摘要翻译：提供肖特基整流器。肖特基整流器包括：（a）具有第一和第二相对面的半导体区域，半导体区域包括邻近第一面的第一导电类型的阴极区域和与第二面相邻的第一导电类型的漂移区域，以及漂移区具有比阴极区更低的净掺杂浓度; （b）从所述第二面延伸到所述半导体区域并限定所述半导体区域内的一个或多个台面的一个或多个沟槽; （c）与沟槽下部的半导体区相邻的绝缘区; （d）和阳极电极（i）在第二面处与半导体相邻并形成肖特基整流接触，（ii）与沟槽上部的半导体区域相邻并形成肖特基整流接触，以及（iii）与沟槽下部的绝缘区域相邻。

3. 发明授权

US06548860B1 DMOS transistor structure having improved performance 有权
标题翻译： DMOS晶体管结构具有改进的性能
公开(公告)号：US06548860B1
公开(公告)日：2003-04-15
申请号：US09515335
申请日：2000-02-29
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0865 , H01L29/1095 , H01L29/7811
摘要： A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.
摘要翻译：提供沟槽DMOS晶体管结构，其包括形成在第一导电类型的衬底上的至少三个单独沟槽DMOS晶体管单元。多个独立的DMOS晶体管单元可分为外围晶体管单元和内部晶体管单元。每个单独的晶体管单元包括位于基板上的体区，其具有第二导电类型。至少一个沟槽延伸穿过身体区域和衬底。绝缘层对沟槽进行排列。导电电极位于沟槽中，覆盖绝缘层。内部晶体管单元，但不是外围晶体管单元，每个还包括与沟槽相邻的体区中的第一导电类型的源极区域。

4. 发明授权

US5877529A Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness 失效
标题翻译： Mosfet终端设计和核心单元配置，以增加击穿电压并提高器件的耐用性
公开(公告)号：US5877529A
公开(公告)日：1999-03-02
申请号：US978667
申请日：1997-11-26
申请人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
发明人： Koon Chong So , Danny Chi Nim , Fwu-Iuan Hshieh , Yan Man Tsui , True-Lon Lin , Shu-Hui Cheng
IPC分类号： H01L29/06 , H01L29/10 , H01L29/78 , H01L29/76 , H01L23/58 , H01L29/94
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/7811 , H01L29/0696 , H01L2924/0002
摘要： Improved power MOSFET structure, and fabrication process are disclosed in this invention to achieve higher breakdown voltage and improved device ruggedness. The power transistor includes a core cell area which includes a plurality of power transistor cells and a termination area. The power transistor further includes an outer pickup guarding ring, disposed in the termination area guarding the core cell area, for picking up free charged-particles generated in the termination area for preventing the free charged particles from entering the core cell area. In another preferred embodiment, the power transistor further includes an inner pickup guarding fence and blocks, disposed between the termination area and the core cell area for picking up free charged-particles not yet picked up by the outer pickup guarding ring for preventing the free charged particles from entering the core cell area.
摘要翻译：在本发明中公开了改进的功率MOSFET结构和制造工艺，以实现更高的击穿电压和改进的器件耐用性。功率晶体管包括包含多个功率晶体管单元和端接区域的核心单元区域。功率晶体管还包括外部拾波器保护环，设置在保护核心单元区域的端接区域中，用于拾取终止区域中产生的免费带电粒子，以防止自由带电粒子进入核心单元区域。在另一个优选实施例中，功率晶体管还包括内部拾取器防护栅栏和块，其设置在终端区域和核心单元区域之间，用于拾取由外部拾音器保护环尚未拾取的免费带电粒子，以防止自由充电颗粒进入核心区域。

5. 发明授权

US06475884B2 Devices and methods for addressing optical edge effects in connection with etched trenches 有权
标题翻译：用于寻址与蚀刻沟槽有关的光学边缘效应的设备和方法
公开(公告)号：US06475884B2
公开(公告)日：2002-11-05
申请号：US09924855
申请日：2001-08-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui
IPC分类号： H01L2136
CPC分类号： H01L29/7813 , H01L21/3083 , H01L29/7811
摘要： In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity type in the body region adjacent to the each internal trench, but not adjacent to the at least one peripheral trench.
摘要翻译：在本发明的第一方面中，提供了一种改进的半导体衬底。改性基板包括：（1）半导体衬底; （2）在衬底的至少一部分上提供的至少一个缓冲层; 和（3）多个沟槽，包括（a）延伸到半导体衬底中的多个内部沟槽和（b）延伸到至少一个缓冲层中但不延伸到半导体衬底中的至少一个浅外围沟槽。另一方面，提供了一种在半导体衬底中选择性地提供沟槽的方法。根据本发明的另一方面，提供了包括至少一个外围沟槽和多个内部沟槽的沟槽DMOS晶体管结构。该结构包括：（1）第一导电类型的衬底; （2）具有第二导电类型的衬底上的主体区域，其中所述外围和内部沟槽延伸穿过所述身体区域; （3）对每个外围和内部沟槽进行排列的绝缘层; （4）覆盖每个绝缘层的第一导电电极; 和（5）与所述每个内部沟槽相邻但不与所述至少一个周边沟槽相邻的所述主体区域中的所述第一导电类型的源极区域。

6. 发明授权

US6048759A Gate/drain capacitance reduction for double gate-oxide DMOS without degrading avalanche breakdown 失效
标题翻译：双栅极氧化物DMOS的栅极/漏极电容降低而不降低雪崩击穿
公开(公告)号：US6048759A
公开(公告)日：2000-04-11
申请号：US21879
申请日：1998-02-11
申请人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui , Danny Chi Nim
发明人： Fwu-Iuan Hshieh , Koon Chong So , Yan Man Tsui , Danny Chi Nim
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/42368 , H01L29/7802 , H01L29/0638
摘要： This invention discloses a DMOS power device supported on a substrate of a first conductivity type functioning as a drain. The DMOS power device includes a polysilicon-over-double-gate-oxide gate disposed on the substrate includes a polysilicon layer disposed over a double-gate-oxide structure having a central thick-gate-oxide segment surrounded by a thin-gate-oxide layer with a thickness of about one-fourth to one-half of a thickness of the thick-gate-oxide segment. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate underneath the thin-gate-oxide layer around edges of the central thick-gate-oxide segment the body region extending out laterally to a neighboring device circuit element. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate encompassed in the body region having a portion extending laterally underneath the thin-gate-oxide layer. The DMOS power device further includes an insulation layer covering the polysilicon-over-double-gate-oxide gate with contact openings above the substrate exposing the source region and the body region.
摘要翻译：本发明公开了一种DMOS功率器件，其被支撑在用作漏极的第一导电类型的衬底上。 DMOS功率器件包括设置在衬底上的多晶硅 - 双栅极氧化物栅极，其包括设置在双栅极 - 氧化物结构上的多晶硅层，其具有由薄栅氧化物围绕的中心厚栅氧化层段厚度为厚栅极 - 氧化物段的厚度的大约四分之一到一半的层。 DMOS功率器件还包括第二导电类型的主体区域，其设置在薄栅氧化层下方的衬底中，围绕中心厚栅氧化物段的边缘，主体区域横向延伸到相邻的器件电路元件。 DMOS功率器件还包括设置在基体中的第一导电类型的源极区域，该基极包含在具有在薄栅氧化层下方横向延伸的部分的主体区域中。 DMOS功率器件还包括覆盖多晶硅超双栅极氧化物栅极的绝缘层，其具有暴露源极区域和体区域的衬底上方的接触开口。

7. 发明授权

US5923065A Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings 失效
标题翻译：功率MOSFET器件采用简化的制造工艺制造，以实现更好的耐用性和产品成本节省
公开(公告)号：US5923065A
公开(公告)日：1999-07-13
申请号：US661952
申请日：1996-06-12
申请人： Koon Chong So , Danny Chi Nim , True-Lon Lin , Fwu-Iuan Hshieh , Yan Man Tsui
发明人： Koon Chong So , Danny Chi Nim , True-Lon Lin , Fwu-Iuan Hshieh , Yan Man Tsui
IPC分类号： H01L21/336 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/7811 , H01L29/0619 , H01L29/0638 , H01L29/402
摘要： This invention discloses a MOSFET device in a semiconductor chip with a top surface and a bottom surface. The MOSFET device includes a drain region, doped with impurities of a first conductivity type, formed in the semiconductor chip near the bottom surface. The MOSFET device further includes a vertical pn-junction region, which includes a lower-outer body region, doped with impurities of a second conductivity type, formed on top of the drain region. The pn-junction region further includes a source region, doped with impurities of the first conductivity type, formed on top of the lower-outer body region wherein the lower-outer body region defining a channel region extending from the source region to the drain region near the top surface. The MOSFET device further includes a gate formed on top of the channel region on the top surface. The gate includes a thin insulative bottom layer for insulating from the channel region. The gate is provided for applying a voltage thereon for controlling a current flowing from the source region to the drain region via the channel region. The MOSFET device further includes a deep heavily doped body-dopant region disposed immediately below the source region in the lower-outer body region. It is implanted with a higher concentration of dopant than the lower-outer body region whereby a device ruggedness of the MOSFET device is improved. The deep heavily-doped body-dopant region having a body-dopant concentration profile defined by a diffusion of the body-dopant from an implant depth about twice as that of a source implant-depth whereby the deep heavily-doped body dopant region is kept at a distance away from the channel region.
摘要翻译：本发明公开了一种具有顶表面和底表面的半导体芯片中的MOSFET器件。 MOSFET器件包括在底表面附近形成在半导体芯片中的掺杂有第一导电类型的杂质的漏极区域。 MOSFET器件还包括垂直pn结区域，其包括形成在漏极区域的顶部上的掺杂有第二导电类型的杂质的下外部体区域。 pn结区域还包括掺杂有第一导电类型的杂质的源区，形成在下外体区域的顶部，其中下外体体区限定从源区延伸到漏区的沟道区靠近顶面。 MOSFET器件还包括形成在顶表面上的沟道区域的顶部上的栅极。栅极包括用于与沟道区绝缘的薄绝缘底层。栅极用于在其上施加电压以控制经由沟道区域从源极区域流到漏极区域的电流。 MOSFET器件还包括深下部重掺杂体 - 掺杂区域，其设置在下外体区域中的源极区域的正下方。注入比下外体区域更高浓度的掺杂剂，从而提高MOSFET器件的器件耐用性。深掺杂的体 - 掺杂剂区域具有由植入深度约为原始植入深度的两倍的体掺杂物的扩散所限定的体 - 掺杂物浓度分布，从而保留深重掺杂体掺杂区域距离通道区域一定距离。

8. 发明授权

US5668026A DMOS fabrication process implemented with reduced number of masks 失效
标题翻译： DMOS制造工艺以减少数量的掩模实现
公开(公告)号：US5668026A
公开(公告)日：1997-09-16
申请号：US611745
申请日：1996-03-06
申请人： True-Lon Lin , Fwu-Iuan Hshieh , Danny Chi Nim , Koon Chong So , Yan Man Tsui
发明人： True-Lon Lin , Fwu-Iuan Hshieh , Danny Chi Nim , Koon Chong So , Yan Man Tsui
IPC分类号： H01L21/265 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/1095 , H01L29/66712 , H01L29/7813 , H01L29/0847 , H01L29/41766
摘要： A new DMOS fabrication process is disclosed. The fabrication process includes the steps of (a) growing an oxide layer on the substrate; (b) applying a first mask to define an active area and for selectively patterning the oxide layer for keeping a plurality of source implant blocking stumps near a plurality source regions wherein the blocking stumps being formed with width greater than twice a diffusion length of a source dopant and with width less than twice a diffusion length of the body dopant whereby the body regions merging together in the body diffusion becoming a single body region underneath the blocking stumps; (c) applying a second mask for forming a plurality of gates covering a portion of areas between the blocking stumps defining an implant window; (d) implanting a body dopant through the implant window followed by a body diffusion for forming a body region underneath the blocking stumps; (e) implanting the source dopant through the implant window over the source implant blocking stumps following by a source diffusion for forming separate source regions underneath the blocking stumps; (f) depositing an insulating dielectric BPSG/PSG layer; (g) employing a contact mask for etching through the insulating dielectric BPSG/PSG layer and the source implant blocking stumps to define contact windows; (h) depositing a metal layer to form a contact layer through the contact window; and (i) patterning the metal layer with a metal contact to define a plurality of contacts whereby the transistor is fabricated with a four masks process.
摘要翻译：公开了一种新的DMOS制造工艺。制造工艺包括以下步骤：（a）在衬底上生长氧化物层; （b）施加第一掩模以限定有源区域并且用于选择性地图案化氧化物层，以便在多个源区域附近保持多个源注入阻挡块，其中形成的阻挡树脂的宽度大于源的扩散长度的两倍掺杂剂并且具有小于体掺杂物的扩散长度的两倍的宽度，从而身体区域在体扩散中合并在一起成为阻塞树桩下方的单个体区域; （c）施加第二掩模以形成覆盖限定植入窗口的阻挡树脂之间的区域的一部分的多个栅极; （d）通过植入窗口植入体内掺杂剂，随后进行体扩散，以形成阻挡树脂下面的体区; （e）在源极注入之后，通过源极扩散将源极掺杂剂注入到植入物窗口上，随后通过源极扩散在阻挡树脂下方形成分离的源区; （f）沉积绝缘介电BPSG / PSG层; （g）使用接触掩模通过绝缘电介质BPSG / PSG层和源极注入阻挡块蚀刻以限定接触窗口; （h）沉积金属层以通过所述接触窗形成接触层; 和（i）用金属接触图案化金属层以限定多个触点，由此通过四个掩模工艺制造晶体管。

9. 发明授权

US07015125B2 Trench MOSFET device with polycrystalline silicon source contact structure 失效
公开(公告)号：US07015125B2
公开(公告)日：2006-03-21
申请号：US10983490
申请日：2004-11-08
申请人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
发明人： Fwu-Iuan Hshieh , Koon Chong So , John E. Amato , Yan Man Tsui
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/456
摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

10. 发明授权

US06762098B2 Trench DMOS transistor with embedded trench schottky rectifier 有权
标题翻译：沟槽DMOS晶体管采用嵌入式沟道肖特基整流器
公开(公告)号：US06762098B2
公开(公告)日：2004-07-13
申请号：US10448791
申请日：2003-05-30
申请人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
发明人： Fwu-Iuan Hshieh , Yan Man Tsui , Koon Chong So
IPC分类号： H01L21336
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/7806 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.
摘要翻译：一种在一个或多个整流器区域内具有多个沟道肖特基势垒整流器的集成电路以及一个或多个晶体管区域内的多个沟槽DMOS晶体管。集成电路包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的掺杂水平; （c）晶体管区域中的外延层内的第二导电类型的多个体区; （d）在所述晶体管区域和所述整流器区域中的所述外延层内的多个沟槽;（e）对所述沟槽进行排列的第一绝缘层; （f）沟槽内的多晶硅导体并覆盖第一绝缘层; （g）在与所述沟槽相邻的位置处的所述主体区域内的所述第一导电类型的多个源极区域; （h）晶体管区域上的掺杂多晶硅层上的第二绝缘层; 和（i）在晶体管区域和整流器区域上的电极层。

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