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41. 发明授权

US07706199B2 Circuit and method for parallel test of memory device 失效
标题翻译：存储器件并行测试电路及方法
公开(公告)号：US07706199B2
公开(公告)日：2010-04-27
申请号：US12000123
申请日：2007-12-10
申请人： Young-Jun Ku , Kee-Teok Park
发明人： Young-Jun Ku , Kee-Teok Park
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C2029/2602
摘要： A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.
摘要翻译：存储器件中的测试电路包括：第一压缩单元，被配置为压缩多个单元的数据以将第一压缩数据发送到多个输入/输出线;以及第二压缩单元，被配置为压缩多个单元上的第一压缩数据输出/输出线以将第二压缩数据输出到至少一个输出引脚，其中响应于数据压缩选择信号，第二压缩单元以低压缩模式和高压缩模式操作。

42. 发明授权

US07619937B2 Semiconductor memory device with reset during a test mode 有权
标题翻译：半导体存储器件，在测试模式下复位
公开(公告)号：US07619937B2
公开(公告)日：2009-11-17
申请号：US11819819
申请日：2007-06-29
申请人： Tae-Sik Yun , Kee-Teok Park
发明人： Tae-Sik Yun , Kee-Teok Park
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/20 , G11C29/1201 , G11C29/46
摘要： A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry.
摘要翻译：半导体存储器件通过在测试模式下通过地址引脚输入的信号在晶片状态下执行复位操作。半导体存储器件包括用于响应于复位有效信号和测试复位信号传送复位指令的缓冲器，用于响应于测试复位信号产生内部测试复位输入信号的测试复位输入信号产生单元以及用于驱动缓冲器的输出信号的有效信号和内部测试复位输入信号的休息信号驱动单元作为复位模式输入的内部复位信号。

43. 发明申请

US20090013225A1 TEST MODE CONTROL CIRCUIT 失效
标题翻译：测试模式控制电路
公开(公告)号：US20090013225A1
公开(公告)日：2009-01-08
申请号：US12209966
申请日：2008-09-12
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31701
摘要： Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.
摘要翻译：提供了一种测试模式控制电路，其能够在测试模式进入之后防止在测试模式退出中的MRS（模式寄存器组）改变。在测试模式控制电路中，MRS控制器逻辑地组合MRS信号，存储体地址，MRS地址和测试模式控制信号以输出锁存控制信号。测试模式控制单元检测测试模式条目和测试模式退出以选择性地激活测试模式设置信号和测试模式退出信号之一，并且根据所述测试模式输入和测试模式退出信号的激活状态输出具有不同电压电平的测试模式控制信号测试模式设置信号或测试模式退出信号。当激活MRS信号时，地址锁存器锁存输入地址，并且当锁存控制信号被激活时，输出锁存的输入地址作为MRS地址。

44. 发明授权

US07447089B2 Bitline precharge voltage generator 有权
标题翻译：位线预充电电压发生器
公开(公告)号：US07447089B2
公开(公告)日：2008-11-04
申请号：US11517351
申请日：2006-09-08
申请人： Jae-Hyuk Im , Kee-Teok Park
发明人： Jae-Hyuk Im , Kee-Teok Park
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/4094
摘要： A bitline precharge voltage generator can generate multiple bitline precharge voltages when bitlines are precharged, thereby providing a stable operation regardless of a core voltage used as a high data voltage of a memory cell. In the bitline precharge voltage generator, a core voltage level detecting unit detects a core voltage level, activates a first enable signal when the core voltage level is lower than a specific voltage level, and activates a second enable signal when the core voltage level is higher than the specific voltage level. A bitline precharge voltage generating unit generates a bitline precharge voltage corresponding to half of the core voltage level when the first enable signal is activated. A bitline precharge voltage clamping unit generates a clamped bitline precharge voltage having a constant voltage level when the second enable signal is activated, regardless of the core voltage level.
摘要翻译：当位线被预充电时，位线预充电电压发生器可以产生多个位线预充电电压，从而提供稳定的操作，而不管用作存储器单元的高数据电压的核心电压。在位线预充电电压发生器中，核心电压电平检测单元检测核心电压电平，当核心电压电平低于特定电压电平时激活第一使能信号，并且当核心电压电平较高时激活第二使能信号比具体的电压电平。位线预充电电压产生单元在第一使能信号被激活时产生对应于核心电压电平的一半的位线预充电电压。位线预充电电压钳位单元产生在第二使能信号被激活时具有恒定电压电平的钳位位线预充电电压，而与核心电压电平无关。

45. 发明授权

US07434120B2 Test mode control circuit 失效
标题翻译：测试模式控制电路
公开(公告)号：US07434120B2
公开(公告)日：2008-10-07
申请号：US11323382
申请日：2005-12-29
申请人： Ji-Eun Jang , Kee-Teok Park
发明人： Ji-Eun Jang , Kee-Teok Park
IPC分类号： G11C29/00
CPC分类号： G01R31/31701
摘要： Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.
摘要翻译：提供了一种测试模式控制电路，其能够在测试模式进入之后防止在测试模式退出中的MRS（模式寄存器组）改变。在测试模式控制电路中，MRS控制器逻辑地组合MRS信号，存储体地址，MRS地址和测试模式控制信号以输出锁存控制信号。测试模式控制单元检测测试模式输入和测试模式退出以选择性地激活测试模式设置信号和测试模式退出信号之一，并且根据所述测试模式输入和测试模式退出信号的激活状态输出具有不同电压电平的测试模式控制信号测试模式设置信号或测试模式退出信号。当激活MRS信号时，地址锁存器锁存输入地址，并且当锁存控制信号被激活时，输出锁存的输入地址作为MRS地址。

46. 发明申请

US20070153603A1 Boosted voltage level detector in semiconductor memory device 有权
标题翻译：半导体存储器件中升压电压检测器
公开(公告)号：US20070153603A1
公开(公告)日：2007-07-05
申请号：US11647127
申请日：2006-12-29
申请人： Kee-Teok Park
发明人： Kee-Teok Park
IPC分类号： G11C7/04
CPC分类号： G11C5/145 , G11C5/143
摘要： A voltage level of a boosted voltage is prevented from being targeted at voltage level that is too low, thereby improving a write recovery time (tWR) characteristic in a memory in a semiconductor memory device. The boosted voltage level detector includes: a voltage divider for dividing a boosted voltage and outputting a divided voltage; and a comparison unit for comparing a reference voltage corresponding to a voltage level of a target voltage with the divided voltage and outputting a level detecting signal, wherein the voltage divider includes: a first voltage drop element connected between a boosted voltage terminal and an output terminal of the voltage divider, having a negative temperature coefficient; and a second voltage drop element connected between the output terminal of the voltage divider and a ground voltage terminal, having a positive temperature coefficient.
摘要翻译：防止升压电压的电压电平被目标为太低的电压电平，从而提高半导体存储器件的存储器中的写恢复时间（tWR）特性。升压电压检测器包括：分压器，用于分压升压电压并输出分压; 以及比较单元，用于将与目标电压的电压电平相对应的参考电压与分压电压进行比较，并输出电平检测信号，其中分压器包括：连接在升压电压端子和输出端子之间的第一压降元件的分压器，具有负温度系数; 以及连接在分压器的输出端子和具有正温度系数的接地电压端子之间的第二电压降元件。

47. 发明申请

US20070070780A1 Output driving device 有权
标题翻译：输出驱动装置
公开(公告)号：US20070070780A1
公开(公告)日：2007-03-29
申请号：US11477481
申请日：2006-06-30
申请人： Kee-Teok Park
发明人： Kee-Teok Park
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C7/1051 , G11C7/1069
摘要： An output driving device includes a pull-up driver for pull-up driving an output node in response to a pull-up control signal; a pull-down driver for pull-down driving the output node in response to a pull-down control signal; and a first n-type metal oxide semiconductor (NMOS) transistor for pull-up driving the output node in response to a pre-pull-up control signal.
摘要翻译：输出驱动装置包括：上拉驱动器，用于响应于上拉控制信号上拉驱动输出节点; 下拉驱动器，用于响应于下拉控制信号下拉驱动输出节点; 以及第一n型金属氧化物半导体（NMOS）晶体管，用于响应于预上拉控制信号上拉驱动输出节点。

48. 发明授权

US07075833B2 Circuit for detecting negative word line voltage 有权
标题翻译：用于检测负字线电压的电路
公开(公告)号：US07075833B2
公开(公告)日：2006-07-11
申请号：US10872346
申请日：2004-06-18
申请人： Khil Ohk Kang , Kee Teok Park
发明人： Khil Ohk Kang , Kee Teok Park
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C29/021 , G11C29/02 , G11C2029/1202 , G11C2029/5004
摘要： The present invention discloses a circuit for detecting a negative word line voltage including a detecting unit for detecting a negative word line voltage in a detection node by using a plurality of loads coupled in series between a power supply terminal and a negative word line voltage terminal, a test signal generating unit for generating a plurality of test signals for detecting variations of the negative word line voltage, and a control unit driven according to the test signals, for controlling a potential of the detection node by adjusting a number of the loads of the detecting unit. The circuit for detecting the negative word line voltage can detect a wanted level of negative word line voltage by using the plurality of test signals without modifying the circuit, to reduce a development period of DRAM semiconductor products.
摘要翻译：本发明公开了一种用于检测负字线电压的电路，包括检测单元，用于通过使用串联耦合在电源端子和负字线电压端子之间的多个负载来检测检测节点中的负字线电压，测试信号产生单元，用于产生用于检测负字线电压的变化的多个测试信号，以及根据测试信号驱动的控制单元，用于通过调整检测节点的数量来控制检测节点的电位检测单元。用于检测负字线电压的电路可以通过使用多个测试信号来检测负字线电压的有用电平而不修改电路，以减少DRAM半导体产品的显影周期。

49. 发明申请

US20050270868A1 Semiconductor memory device and method for adjusting internal voltage thereof 失效
标题翻译：半导体存储器件及其内部电压调节方法
公开(公告)号：US20050270868A1
公开(公告)日：2005-12-08
申请号：US11000083
申请日：2004-12-01
申请人： Jae-Hyuk Im , Kee-Teok Park
发明人： Jae-Hyuk Im , Kee-Teok Park
IPC分类号： G11C5/14 , G11C7/00 , G11C29/00 , G11C29/02
CPC分类号： G11C29/021 , G11C29/02 , G11C29/028 , G11C2029/5004
摘要： A semiconductor memory device improves test reliability by suppressing unnecessary leakage component in a USMC test which checks if data is normally transferred by extending a time margin between an active signal input time and a bit line sensing time. The semiconductor memory device includes at least one inner voltage adjusting unit for adjusting an inner voltage for limiting leakage portion that is generated in the semiconductor memory device during the USMC test by using a USMC signal for starting the USMC test and a termination signal for terminating the USMC test. The inner voltage adjusting unit includes a bulk bias voltage adjusting unit for supplying a bulk bias voltage to a cell transistor in the semiconductor memory device.
摘要翻译：半导体存储器件通过在USMC测试中抑制不必要的泄漏分量来提高测试的可靠性，USMC测试通过延长有源信号输入时间和位线检测时间之间的时间间隔来检查数据是否正常传输。半导体存储器件包括至少一个内部电压调节单元，用于在USMC测试期间通过使用USMC信号来调节在半导体存储器件中产生的用于限制泄漏部分的内部电压，以启动USMC测试，以及终止信号 USMC测试。内部电压调节单元包括用于向半导体存储器件中的单元晶体管提供体偏置电压的体偏置电压调整单元。

50. 发明申请

US20050231251A1 Apparatus and method for adjusting slew rate in semiconductor memory device 有权
标题翻译：用于调整半导体存储器件中的转换速率的装置和方法
公开(公告)号：US20050231251A1
公开(公告)日：2005-10-20
申请号：US11022840
申请日：2004-12-28
申请人： Jae-Hyuk Im , Kee-Teok Park
发明人： Jae-Hyuk Im , Kee-Teok Park
IPC分类号： G11C7/10 , G11C29/02 , H03M1/12
CPC分类号： G11C29/028 , G11C29/02 , G11C29/50012
摘要： A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver for adjusting a slew rate of a data signal by changing the number of switching elements turned on in response to the slew-rate modulation signal.
摘要翻译：一种用于半导体存储器件的转换速率调节装置包括：转换速率调制信号发生器，用于根据多个控制码中具有第一逻辑电平的控制码的数量产生转换速率调制信号，在外部可编程; 以及预驱动器，用于通过响应于压摆率调制信号改变导通的开关元件的数量来调整数据信号的转换速率。

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