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    • 44. 发明申请
    • METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR CONSTRAINT VERIFICATION FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRICAL AWARENESS
    • 用于实现电子电路设计的电路认证的制造方法,系统和制造与电气意识
    • US20120023468A1
    • 2012-01-26
    • US12982732
    • 2010-12-30
    • Ed FISCHERMichael MCSHERRYDavid WHITEBruce YANAGIDAAkshat SHAH
    • Ed FISCHERMichael MCSHERRYDavid WHITEBruce YANAGIDAAkshat SHAH
    • G06F17/50
    • G06F17/5081G06F17/5068G06F17/5077
    • Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.
    • 公开了用于实现具有电气意识的电子电路设计的约束验证的方法,系统和制造。 一些实施例识别或设置寄生约束,并将电子寄生与相应的寄生约束进行比较,以确定是否满足寄生约束。 一些实施例首先识别,确定或更新部分布局的部件的物理数据,并表征与部件的物理数据相关联的电寄生效应。 一些实施例基于示意性模拟结果和性能约束来识别或确定一些示意图级性能约束并且估计寄生约束; 然后将估计的寄生约束与相应的电寄生效应进行比较,以确定是否满足约束。 一些实施例还将原理层级寄生约束映射到物理设计表示,然后将映射的寄生约束与对应的电限制进行比较,以确定是否满足映射的约束。
    • 47. 发明申请
    • Splint for treatment of musculoskeletal injury of the hand
    • 夹板用于治疗手骨的肌肉骨骼损伤
    • US20110245747A1
    • 2011-10-06
    • US12929877
    • 2011-02-22
    • Ronit WollsteinThomas OgdenJonathan PearlmanRory A. CooperDavid WhiteMiriam Zisook
    • Ronit WollsteinThomas OgdenJonathan PearlmanRory A. CooperDavid WhiteMiriam Zisook
    • A61F5/00
    • A61F5/10A61F5/05875A61F2005/0197
    • A splint for treatment of a joint including a generally longitudinal body including first and second portions forming inner and outer splint layers, with the second portion being rollable onto the first portion to form the splint. The outer splint layer may include a longitudinal cavity for insertion of a stay, and/or may include a fluted section for permitting insertion of a stay between the inner and outer splint layers. The longitudinal body may be linear or curved. The first and second portions may include areas having different thicknesses for adding rigidity to the splint structure at a predetermined location. The splint may include a cutout for exposing a predetermined portion of a user's finger. The splint may be made of a flexible material such as rubber, silicone and/or urethane. The splint may include a reduced friction surface layer for minimizing sticking of the splint during donning.
    • 一种用于治疗关节的夹板,包括大体上纵向的主体,包括形成内部和外部夹板层的第一和第二部分,第二部分可滚动到第一部分上以形成夹板。 外夹板层可以包括用于插入支柱的纵向腔,和/或可以包括用于允许在内夹板和外夹板层之间插入支柱的带槽部分。 纵向体可以是线性的或弯曲的。 第一和第二部分可以包括具有不同厚度的区域,用于在预定位置向夹板结构增加刚度。 夹板可以包括用于暴露用户手指的预定部分的切口。 夹板可以由诸如橡胶,硅树脂和/或聚氨酯的柔性材料制成。 夹板可以包括减少的摩擦表面层,以最小化穿戴期间夹板的粘附。
    • 48. 发明授权
    • Electronic design for integrated circuits based on process related variations
    • 基于过程相关变化的集成电路的电子设计
    • US07962867B2
    • 2011-06-14
    • US12021298
    • 2008-01-28
    • David WhiteTaber H. Smith
    • David WhiteTaber H. Smith
    • G06F17/50
    • G06F17/5068H01L21/31053H01L21/3212
    • An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
    • 产生电子设计,用于根据电子设计制造的集成电路,该集成电路将通过将集成电路赋予地形诱导的特征尺寸变化的过程。 该生成包括基于模式相关模型基于地形和地形相关特征维度变化的预测来调整电子设计。 RC提取工具与电子设计的生成和调整结合使用。 该方法包括将赋予集成电路的拓扑变化和光刻或蚀刻工艺的制造工艺。 确定集成电路元件的放置属性。