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41. 发明授权

US5578517A Method of forming a highly transparent silicon rich nitride protective layer for a fuse window 失效
标题翻译：形成用于保险丝窗的高度透明的富氮氮化物保护层的方法
公开(公告)号：US5578517A
公开(公告)日：1996-11-26
申请号：US328587
申请日：1994-10-24
申请人： Chue-San Yoo , Jin-Yuan Lee
发明人： Chue-San Yoo , Jin-Yuan Lee
IPC分类号： H01L21/768 , H01L23/31 , H01L23/525 , H01L27/02 , H01L27/00 , H01L21/70
CPC分类号： H01L27/0248 , H01L21/76888 , H01L23/3171 , H01L23/5258 , H01L2924/0002 , Y10S148/055 , Y10S438/94
摘要： An integrated circuit includes a conductive fusible link that may be blown by heating with laser irradiation. The integrate circuit comprises: a silicon substrate; a first insulating layer; a fusible link on the first layer; a second insulating layer overlying the first layer and the fusible link; an opening through the second layer exposing the fuse; and a protective layer over the surfaces of the opening. A laser beam is irradiated through the opening and the protective layer to melt the fusible link. The protective layer is highly transparent to a laser beam and does not interfere with the laser melting (trimming) operation. Moreover, the protective layer prevents contaminates from diffusing in through the opening to harm adjacent semiconductor devices.
摘要翻译：集成电路包括可以通过用激光照射加热而被吹送的导电性可熔连接件。集成电路包括：硅衬底; 第一绝缘层; 第一层的易熔连接; 覆盖在第一层和熔丝上的第二绝缘层; 穿过第二层的开口露出保险丝; 以及在开口表面上的保护层。通过开口和保护层照射激光束以熔化可熔链。保护层对于激光束是高度透明的，并且不干扰激光熔化（修整）操作。此外，保护层防止污染物通过开口扩散以损害相邻的半导体器件。

42. 发明授权

US5393685A Peeling free metal silicide films using rapid thermal anneal 失效
标题翻译：使用快速热退火剥离游离金属硅化物膜
公开(公告)号：US5393685A
公开(公告)日：1995-02-28
申请号：US926299
申请日：1992-08-10
申请人： Chue-San Yoo , Ting-Hwang Lin
发明人： Chue-San Yoo , Ting-Hwang Lin
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28518
摘要： A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which provides a peeling-free metal silicide gate electrode devices. The process uses annealing of the gate oxide, the polysilicon layer and the metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000.degree. C. and for a time of between about 30 to 60 seconds. A pattern of lightly doped regions is formed in the substrate by ion implantation using the structures as the mask. A low temperature silicon dioxide layer is blanket deposited over the surfaces of the structure. The blanket layer is etched to form a dielectric spacer structure upon the sidewalls of each of the gate electrode structures and over the adjacent portions of the substrate, and to remove the silicon oxide layer from the top surfaces of metal silicide layer. Driving in the pattern of lightly doped regions is accomplished by rapid thermal annealing at a temperature of more than about 1000.degree. C. and for a time of between about 30 to 60 seconds with the metal silicide layer having no covering thereover. Heavily doped regions are now formed in the substrate to produce the lightly doped drain under the spacer structure of an MOS FET device. A passivation layer is formed over the structures and electrical connecting structures thereover.
摘要翻译：描述了一种制造提供无剥离金属硅化物栅电极器件的轻掺杂漏极MOSFET集成电路器件的方法。该方法使用快速热退火工艺在大于约1000℃的温度和大约30至60秒的时间内对栅极氧化物，多晶硅层和金属硅化物层进行退火。通过使用该结构作为掩模的离子注入在衬底中形成轻掺杂区域的图案。低温二氧化硅层被覆盖在该结构的表面上。蚀刻覆盖层以在每个栅电极结构的侧壁上和衬底的相邻部分之上形成介电间隔物结构，并从金属硅化物层的顶表面去除氧化硅层。通过在大于约1000℃的温度下快速热退火并且在其间没有覆盖的金属硅化物层的时间为约30至60秒之间来实现轻掺杂区域的驱动。现在在衬底中形成重掺杂区域，以在MOS FET器件的间隔结构之下产生轻掺杂漏极。在其上的结构和电连接结构上形成钝化层。

43. 发明授权

US08268541B2 Mask and blank storage inner gas 有权
标题翻译：面罩和空白存储内部气体
公开(公告)号：US08268541B2
公开(公告)日：2012-09-18
申请号：US11733471
申请日：2007-04-10
申请人： Cheng-Ming Lin , Chue San Yoo
发明人： Cheng-Ming Lin , Chue San Yoo
IPC分类号： G03F7/20
CPC分类号： G03F7/70916 , G03F7/70866
摘要： The present disclosure provides a lithography apparatus. The lithography apparatus includes a radiation source providing a radiation energy with a wavelength selected from the group consisting of 193 nm, 248 nm, and 365 nm; a lens system configured approximate to the radiation source; a mask chamber proximate to the lens system, configured to hold a mask and operable to provide a single atom gas to the mask chamber; and a substrate stage configured to hold a substrate and receive the radiation energy through the lens system and the mask during an exposing process.
摘要翻译：本公开提供一种光刻设备。光刻设备包括：辐射源，其提供波长选自193nm，248nm和365nm的波长的辐射能; 配置为近似于辐射源的透镜系统; 靠近透镜系统的掩模室，被配置为保持掩模并可操作以向掩模室提供单个原子气体; 以及衬底台，被配置为在曝光过程期间保持衬底并且通过透镜系统和掩模接收辐射能量。

44. 发明申请

US20080266534A1 PHOTOMASK HAZE REDUCTION VIA VENTILATION 有权
标题翻译：照片通过通风降低烟雾
公开(公告)号：US20080266534A1
公开(公告)日：2008-10-30
申请号：US11740166
申请日：2007-04-25
申请人： Chue San Yoo
发明人： Chue San Yoo
IPC分类号： G03B27/42
CPC分类号： G03F1/64
摘要： Where a framed pellicle is mounted on a photomask, the framed pellicle comprises a pellicle frame and a pellicle membrane coupled to the pellicle frame, the pellicle frame has first and second apertures each communicating a first space surrounded by the photomask and the framed pellicle with a second space outside of the framed pellicle, exposing a photoresist layer formed on a substrate by flowing gas from within the first space to outside the framed pellicle through the first aperture while simultaneously exposing the photoresist layer to ultraviolet light through the pellicle membrane and the photomask.
摘要翻译：在框架防护薄膜组件安装在光掩模上的情况下，框架防护薄膜组件包括防护薄膜组件框架和联接到防护薄膜框架上的防护薄膜组件，防护薄膜框架具有第一和第二孔，每个孔与光掩模和框架防护薄膜组件包围的第一空间与在框架防护薄膜外部的第二空间，通过将气体从第一空间内流过框架防护薄膜通过第一孔而暴露出形成在基板上的光致抗蚀剂层，同时将光致抗蚀剂层暴露于通过防护薄膜和光掩模的紫外光。

45. 发明授权

US06242341B1 Planarization using laser ablation 有权
公开(公告)号：US06242341B1
公开(公告)日：2001-06-05
申请号：US09332423
申请日：1999-06-14
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L2144
CPC分类号： H01L21/7684 , H01L21/76819
摘要： A process for planarization of a silicon wafer is described together with apparatus for implementing it. The process planarizes by directing a high-energy, pulsed laser beam in a direction parallel to the wafer surface while the wafer is rotating. The height of the beam relative to the wafer is carefully controlled thereby enabling the removal of all material above the lower edge of the beam to be removed from the wafer through laser ablation. The method works equally well for removal of metal (as in planarization of damascene wiring) or dielectric (as in planarization of conventional wiring). Once all excess material has been removed (typically requiring about 60 seconds) additional operation of the process does no harm so neither end point detection nor precise control of process time are required.

46. 发明授权

US06200836B1 Using oxide junction to cut off sub-threshold leakage in CMOS devices 有权
标题翻译：使用氧化物结切断CMOS器件中的亚阈值泄漏
公开(公告)号：US06200836B1
公开(公告)日：2001-03-13
申请号：US09368862
申请日：1999-08-06
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L2100
CPC分类号： H01L29/0653 , H01L21/26533
摘要： A new method is provided for the formation of Lightly Doped Drain (LDD) regions in MOS devices. The body of the gate electrode is formed including the self-aligned LDD regions. After the LDD regions have been formed, an oxide implant is performed under an angle into the surface of the substrate on which the MOS device is being formed. This oxide implant forms an oxide layer around the interface between the source/drain regions and the surrounding silicon. The spacers for the gate electrode are formed, the source/drain region implant is completed. This implanted oxygen junction is subjected to a thermal treatment thereby forming an oxide layer around the source/drain regions. This oxide layer eliminates the leakage current across the interface between the source/drain regions and the surrounding silicon further forcing the saturation current between these regions to flow along the surface of the silicon substrate.
摘要翻译：提供了一种在MOS器件中形成轻掺杂漏极（LDD）区域的新方法。形成包括自对准LDD区域的栅电极的主体。在LDD区域形成之后，在其上形成有MOS器件的衬底的表面上以一定角度进行氧化物注入。这种氧化物注入在源/漏区和周围的硅之间的界面周围形成氧化物层。形成用于栅电极的间隔物，完成源极/漏极区域注入。对该注入的氧结进行热处理，从而在源/漏区周围形成氧化物层。该氧化物层消除了源极/漏极区域和周围硅之间的界面处的漏电流，进一步迫使这些区域之间的饱和电流沿着硅衬底的表面流动。

47. 发明授权

US06168984A Reduction of the aspect ratio of deep contact holes for embedded DRAM devices 有权
标题翻译：降低嵌入式DRAM器件深度接触孔的长宽比
公开(公告)号：US06168984A
公开(公告)日：2001-01-02
申请号：US09419103
申请日：1999-10-15
申请人： Chue-San Yoo , Ming-Hsiung Chiang , Wen-Chuan Chiang , Cheng-Ming Wu , Tse-Liang Ying
发明人： Chue-San Yoo , Ming-Hsiung Chiang , Wen-Chuan Chiang , Cheng-Ming Wu , Tse-Liang Ying
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10814 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A process for reducing the aspect ratio, for narrow diameter contact holes, formed in thick insulator layers, used to integrate logic and DRAM memory devices, on the same semiconductor chip, has been developed. The process of reducing the aspect ratio, of these contact holes, features initially forming, via patterning procedures, lower, narrow diameter contact holes, to active device regions, in the logic area, while also forming self-aligned contact openings to source/drain regions in the DRAM memory region. After forming tungsten structures, in the lower, narrow diameter contact holes, polycide bitline, and polysilicon capacitor structures, are formed in the DRAM memory region, via deposition, and patterning, of upper level insulator layers, and polysilicon and polycide conductive layers. Upper, narrow diameter openings, are then formed in the upper level insulator layers, exposing the top surface of tungsten structures, located in the lower, narrow diameter contact holes. The formation of upper tungsten structures, in the upper, narrow diameter contact openings completes the process of forming metal structures, in narrow diameter openings, with reduced aspect ratios, achieved via a two stage contact hole opening, and a two stage metal filling procedure.
摘要翻译：已经开发了用于在相同的半导体芯片上将用于集成逻辑和DRAM存储器件的厚的绝缘体层中形成的窄直径接触孔的宽高比减小的方法。减小这些接触孔的纵横比的过程，其特征在于，通过图案化步骤，在逻辑区域中最初形成较小的窄直径的接触孔到有源器件区域，同时还形成自对准的接触开口到源极/漏极 DRAM存储区域中的区域。在形成钨结构之后，在下部窄直径的接触孔中，多晶硅位线和多晶硅电容器结构通过上层绝缘体层和多晶硅和多晶硅导电层的沉积和图案形成在DRAM存储区域中。然后在上层绝缘体层中形成上部，小直径的开口，暴露位于下部较窄直径的接触孔中的钨结构的顶表面。在上部窄直径接触开口中形成上部钨结构完成了通过两级接触孔开口形成的具有减小的纵横比的窄直径开口中的金属结构的形成和两阶段金属填充程序的过程。

48. 发明授权

US6071783A Pseudo silicon on insulator MOSFET device 有权
公开(公告)号：US6071783A
公开(公告)日：2000-06-06
申请号：US133353
申请日：1998-08-13
申请人： Mong-Song Liang , Jin-Yuan Lee , Chue-San Yoo
发明人： Mong-Song Liang , Jin-Yuan Lee , Chue-San Yoo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/417
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/41766
摘要： A process for forming a MOSFET device, featuring a heavily doped source/drain region, isolated from a semiconductor substrate, via use of a thin silicon oxide layer, has been developed. After formation of a lightly doped source/drain region, an opening is created in the semiconductor substrate, in a region between insulator spacers, on a gate structure, and insulator filled, shallow trench regions, resulting in lightly doped source/drain segments, remaining under the masking insulator spacers. After a thin silicon oxide layer is formed on the exposed silicon surfaces, in the openings, a silicon deposition, and etch back procedures are performed, partially refilling the openings to a depth that still allows the thin silicon oxide layer to be exposed on the sides of the lightly doped source/drain segment. After removal of the exposed portion of the thin silicon oxide layer, and after deposition and etch back of another silicon layer, completely filling the openings, a heavily doped source/drain region is formed in the silicon layers, residing in the openings.

49. 发明授权

US6025270A Planarization process using tailored etchback and CMP 失效
标题翻译：使用定制回蚀和CMP的平面化过程
公开(公告)号：US6025270A
公开(公告)日：2000-02-15
申请号：US794693
申请日：1997-02-03
申请人： Chue-San Yoo
发明人： Chue-San Yoo
IPC分类号： H01L21/3105 , H01L21/302
CPC分类号： H01L21/31056 , H01L21/31053
摘要： An improved and new method for forming a planarized integrated cirsuit structure has been developed. The method uses a combination of etchback and chemical/mechanical polishing (CMP), in which the etchback process uses a tailored mask to compensate for non-unifomity of material removal by the subsequent chemical/mechanical (CMP) process, thereby resulting in improved planarization and superior thickness uniformity.
摘要翻译：已经开发了一种形成平面化的集成连接结构的改进和新的方法。该方法使用回蚀和化学/机械抛光（CMP）的组合，其中回蚀工艺使用定制的掩模来补偿随后的化学/机械（CMP）工艺去除材料的非一体性，从而导致改进的平坦化并具有优异的厚度均匀性。

50. 发明授权

US5965927A Integrated circuit having an opening for a fuse 有权
标题翻译：具有用于保险丝的开口的集成电路
公开(公告)号：US5965927A
公开(公告)日：1999-10-12
申请号：US157513
申请日：1998-09-21
申请人： Jin-Yuan Lee , Chue-San Yoo , Hsien Wei Chin
发明人： Jin-Yuan Lee , Chue-San Yoo , Hsien Wei Chin
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S148/055
摘要： An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.
摘要翻译：提出了在保险丝上的绝缘层的开口上形成保护层的改进的结构和方法。保护层防止污染物进入保险丝开口中暴露的绝缘层，而不会干扰保险丝的激光修整。形成穿过熔丝的层的开口形成垂直侧壁，其暴露部分绝缘层。在绝缘层，侧壁和熔断体上形成保护层，从而防止污染物扩散到暴露的绝缘层中。在熔断体上方的保护层中形成第二个开口，以允许激光束熔化下面的熔断体。

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