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    • 31. 发明授权
    • System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations
    • 用于配置仪器以利用将图形程序转换成硬件实现来执行测量功能的系统和方法
    • US06219628B1
    • 2001-04-17
    • US08912427
    • 1997-08-18
    • Jeffrey L. KodoskyHugo AndradeBrian K. OdomCary P. Butler
    • Jeffrey L. KodoskyHugo AndradeBrian K. OdomCary P. Butler
    • G06F760
    • G06F8/34G06F11/2294G06F11/2733G06F17/5054G06F2217/74
    • A system and method for configuring an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. A graphical program is first created, wherein the graphical program implements a measurement function. The graphical program may include a front panel and a block diagram. The method then generates a hardware description based on at least a portion of the graphical program. The hardware description describes a hardware implementation of the at least a portion of the graphical program. The method then configures the programmable hardware element in the instrument utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the at least a portion of the graphical program. The instrument then acquires a signal from an external source, and the programmable hardware element in the instrument executes to perform the measurement function on the signal. The front panel may be used by a user to control the instrument during the measurement.
    • 一种用于配置仪器以执行测量功能的系统和方法,其中所述仪器包括可编程硬件元件。 首先创建图形程序,其中图形程序实现测量功能。 图形程序可以包括前面板和框图。 该方法然后基于图形程序的至少一部分生成硬件描述。 硬件描述描述了图形程序的至少一部分的硬件实现。 然后,该方法使用硬件描述来配置仪器中的可编程硬件元件以产生配置的硬件元件。 因此,配置的硬件元件实现图形程序的至少一部分的硬件实现。 然后,仪器从外部源获取信号,并且仪器中的可编程硬件元件执行以对信号执行测量功能。 在测量期间,用户可以使用前面板来控制仪器。
    • 32. 发明授权
    • Hardware-software co-synthesis of embedded system architectures using quality of architecture metrics
    • US06178542B1
    • 2001-01-23
    • US09024846
    • 1998-02-17
    • Bharat P. Dave
    • Bharat P. Dave
    • G06F760
    • G06F9/4887G06F17/5045Y02D10/24
    • Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it employs a combination of preemptive and non-preemptive scheduling, 4) it introduces the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5) it uses a static scheduler based on deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the changing nature of the critical path in the task graph into account, 7) it supports pipelining of task graphs to derive a cost-efficient architecture, 8) it supports a mix of various technologies to meet embedded system constraints and minimize power dissipation, and 9) if desired, it also optimizes the architecture for power consumption. According to one embodiment, during the synthesis phase, the possible allocations are selected based on one or more quality of architecture metrics. The present invention can be applied to constructive or iterative co-synthesis processes, as well as the allocation of tasks in an existing embedded system, where allocation means either assigning tasks to components or scheduling assigned tasks or both.
    • 35. 发明授权
    • Method allowing to obtain an optimum model of a physical characteristic in a heterogeneous medium such as the subsoil
    • 允许在异质介质如底土中获得物理特性的最佳模型的方法
    • US06662147B1
    • 2003-12-09
    • US09548431
    • 2000-04-12
    • Frédérique FournierJean-Jacques Royer
    • Frédérique FournierJean-Jacques Royer
    • G06F760
    • G01V1/282G01V11/00G01V2210/66
    • A method for obtaining, by means of an inversion process, an optimum model of a physical characteristic in a heterogeneous medium (the impedance of an underground zone in relation to waves transmitted in the ground for example), by taking as the starting point an a priori model of the physical characterized that is optimized by minimizing a cost function dependent on differences between the optimized model which is sought and the known data, considering the a priori model. Construction of the a priori model comprises correlation by kriging between values of the physical quantity known at different points of the medium along discontinuities (strata directions). Uncertainties about the values of the physical quantity in the a priori model in relation to the corresponding values in the medium follow a covariance model that controls the inversion parameters more quantitatively. The characteristics of the covariance model are defined in connection with the structure of the data observed or measured in the medium. An application of the optimum model is location of hydrocarbon reservoirs.
    • 通过反演处理获得异质介质中的物理特性的最优模型(地下区域的阻抗相对于在地面中传输的波的阻抗)的方法,以起始点为a 物理特征的先验模型通过考虑先验模型,通过最小化取决于所寻求的优化模型与已知数据之间的差异的成本函数来优化。 先验模型的构造包括通过在不连续性(层数方向)处在介质的不同点处已知的物理量的值之间的克里金相关。 关于先验模型中物理量的值与介质中相应值相关的不确定性遵循更加量化控制反演参数的协方差模型。 协方差模型的特征与介质中观察或测量的数据结构有关。 最佳模型的应用是油气藏的位置。
    • 36. 发明授权
    • Injection mold design system and injection mold design method
    • 注塑模具设计系统和注塑模具设计方法
    • US06618643B2
    • 2003-09-09
    • US09965865
    • 2001-10-01
    • Shusaku NishiyamaShingo YamaguchiTatsuo KimuraMasayuki ImakadoNaoki AsanoFumihiko Makiuchi
    • Shusaku NishiyamaShingo YamaguchiTatsuo KimuraMasayuki ImakadoNaoki AsanoFumihiko Makiuchi
    • G06F760
    • B29C33/3835B29C45/26G05B19/4099G05B2219/35044G05B2219/35078Y02P90/265
    • An injection mold design method for correcting a profile of a product to be fabricated into a releasable profile from a mold to design an injection mold based on a corrected product shape, utilizing a storage device for storing information of the product shape and mold profile, a display device for displaying the product shape or the mold profile on a screen based on the information read from the storage device, an input device for inputting designation information necessary for correction of the product shape or the mold profile, and a controlling device for unloading information of lines or planes being obstructive to correction of the product shape and the mold profile in the storage device in response to the designation information input by the input device. The method comprises removing lines or planes from the screen, and replotting the lines or the planes on the screen in terms of the information of lines or planes unloaded into the storage device after the correction operation of the product shape of the mold profile is completed.
    • 一种注射模具设计方法,用于基于校正的产品形状来校正要从模具制造成可释放轮廓的产品的轮廓的轮廓,利用用于存储产品形状和模具轮廓的信息的存储装置, 显示装置,用于基于从存储装置读取的信息在屏幕上显示产品形状或模具轮廓;输入装置,用于输入用于校正产品形状或模具轮廓所需的指定信息;以及控制装置,用于卸载信息 线或平面响应于由输入装置输入的指定信息而阻碍了存储装置中的产品形状和模具轮廓的校正。 该方法包括:从模具轮廓的产品形状的校正操作完成之后,从屏幕上移除线或平面,以及将屏幕上的线或平面重新划分为在卸载到存储装置中的线或平面的信息。
    • 37. 发明授权
    • Method and apparatus for representing integrated circuit device characteristics using polynomial equations
    • 使用多项式方程表示集成电路器件特性的方法和装置
    • US06615164B1
    • 2003-09-02
    • US09293560
    • 1999-04-15
    • Runip GopisettyGao Feng Wang
    • Runip GopisettyGao Feng Wang
    • G06F760
    • G06F17/5036
    • An approach for representing integrated circuit device characteristics using polynomial equations involves analyzing integrated circuit device characterization data in a lookup table form and using an order incremental scheme to determine a polynomial equation of a relatively low-order that satisfies specified accuracy criteria. In situations where a polynomial equation that has an order less than a maximum allowable order cannot be determined, the integrated circuit device characterization data is partitioned into sub-domains and polynomial equations are determined separately for each sub-domain. The separate polynomial equations are then combined to generate a piecewise polynomial equation that represents all of the integrated circuit device characterization data.
    • 使用多项式方程表示集成电路器件特性的方法包括以查找表格形式分析集成电路器件表征数据,并使用阶增量方案来确定满足指定精度标准的相对低阶的多项式方程。 在不能确定具有小于最大可允许顺序的阶数的多项式方程的情况下,将集成电路器件表征数据划分为子域,并且为每个子域分别确定多项式方程。 然后组合单独的多项式方程以产生表示所有集成电路器件表征数据的分段多项式方程。
    • 39. 发明授权
    • Simulation method of wiring temperature rise
    • 布线温升模拟方法
    • US06513000B1
    • 2003-01-28
    • US09281066
    • 1999-03-10
    • Takeshi Toda
    • Takeshi Toda
    • G06F760
    • G01N25/18G06F17/5018G06F2217/36G06F2217/80H01L23/34H01L2924/0002H01L2924/3011H01L2924/00
    • A heat capacity C1 is obtained by conducting two-dimensional thermal analysis simulation to the cross-section of a wiring. Next, based on one-dimensional approximate equation of &thgr;0=(Q0/2) (&lgr;·SC1)−½ along a wiring length direction, a wiring temperature rise &thgr;0 in the void is obtained. In the expression, &thgr;0 is a rise in wiring temperature in the void, Q0 is a thermal quantity of the void in the wiring, &lgr; is a heat conductivity of the wiring and S is a cross-sectional area of the wiring. The heat capacity C1 may be obtained from an expression C1=&lgr;′{(w/t)+(2.80/1.15) (h/t)0.222}. In the expression, W is wiring width, h is wiring thickness, t is substrate film thickness and &lgr;′ is the heat conductivity of the substrate film. By so obtaining, it is possible to shorten analysis time, to save the capacity of a memory and that of a disk for use in calculation, to obtain a simpler analysis model and to facilitate creating a mesh.
    • 通过对布线的横截面进行二维热分析模拟获得热容C1。 接下来,基于沿着布线长度方向的θ0=(Q0 / 2)(lambd.SC1)-½的一维近似方程,获得空隙中的布线温度升高θ0。 在表达式中,θ0是空隙中布线温度的升高,Q0是布线中的空隙的热量,lambd是布线的热导率,S是布线的横截面积。 热容C1可以从表达式C1 = lambd'{(w / t)+(2.80 / 1.15)(h / t)0.222}获得。 在表达式中,W是布线宽度,h是布线厚度,t是基板膜厚度,lambd'是基板膜的导热率。 通过这样获得,可以缩短分析时间,以节省存储器的容量和用于计算的磁盘的容量,以获得更简单的分析模型并促进创建网格。
    • 40. 发明授权
    • Simulation method and apparatus using a Fourier transform
    • 使用傅立叶变换的仿真方法和装置
    • US06499004B1
    • 2002-12-24
    • US09216982
    • 1998-12-21
    • Shinichi OhtsuMakoto Mukai
    • Shinichi OhtsuMakoto Mukai
    • G06F760
    • G05B17/02G06F17/5036
    • Solving simultaneous equations of the moment method defining relationships between a mutual impedence between elements of an electronic apparatus, a wave source, and an electric current flowing in each element so as to simulate an electric current, provided with a unit for calculating the mutual impedance at a sampling frequency and calculating approximation coefficients, when expressing the mutual impedance by approximation expressions in terms of exponents and exponent powers, from the calculated values and sampling frequency; a unit for forming the simultaneous differential equations by setting the approximation coefficients and initial value with respect to the simultaneous differential equations derived by performing a Fourier transform on the simultaneous equations of the moment method in which the approximation expressions are substituted; and a unit for calculating the electric current in the time domain flowing through the specified element by solving the simultaneous differential equations formed.
    • 求解定义电子装置的元件间的相互阻抗,波源和流过每个元件的电流之间的关系的时刻方法,以便模拟电流,该方法设置有用于计算互阻抗的单位 当从计算值和采样频率表示通过指数和指数幂的近似表达式的互阻抗时,采样频率和计算近似系数; 用于通过对近似表达式被替代的力矩方法的联立方程进行傅里叶变换得到的同步微分方程式来设定近似系数和初始值来形成同步微分方程的单元; 以及通过求解形成的同步微分方程来计算流过指定元件的时域中的电流的单元。