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31. 发明授权

US5557270A Dual conversion decoder 失效
标题翻译：双转换解码器
公开(公告)号：US5557270A
公开(公告)日：1996-09-17
申请号：US295999
申请日：1994-08-25
申请人： Atushi Miyanishi , Hisashi Matsumoto , Yoshiki Tsujihashi
发明人： Atushi Miyanishi , Hisashi Matsumoto , Yoshiki Tsujihashi
IPC分类号： H03M7/00 , H03M7/22 , H03M7/14
CPC分类号： H03M7/22
摘要： A decoder has first and second decoder circuits for producing dual sets of outputs. The first decoder circuit is responsive to input lines B.sub.1 -B.sub.n representative of a binary value x and has first outputs Z.sub.1 -Z.sub.m where m=2.sup.n. In response to the value x applied to the first decoder, output line Z.sub.x+1 is set high while the remainder are set low. The second decoder circuit comprises m transmission gates serially connected between a first and a second potential. The transmission gates are each directly driven by a respective one of said first outputs Z.sub.1 -Z.sub.m. The second decoder circuit generates second outputs Y.sub.1 -Y.sub.m-1 at junctions of the transmission gates. In response to the value x applied to the first decoder, x number of the outputs Y.sub.1 -Y.sub.m-1 are set high beginning with the least significant output Y.sub.1 and continuing consecutively up to the output Y.sub.x with the remainder being set low.
摘要翻译：解码器具有用于产生双组输出的第一和第二解码器电路。第一解码器电路响应表示二进制值x的输入线B1-Bn，并具有第一输出Z1-Zm，其中m = 2n。响应于施加到第一解码器的值x，输出线Zx + 1被设置为高，而余数设置为低。第二解码器电路包括串联连接在第一和第二电位之间的m个传输门。传输门各自由所述第一输出Z1-Zm中的相应一个直接驱动。第二解码器电路在传输门的结点处产生第二输出Y1-Ym-1。响应于施加到第一解码器的值x，从最低有效输出Y1开始将x个输出Y1-Ym-1设置为高，并且连续地连续地输出余数被设置为低的输出Yx。

32. 发明授权

US4758744A Decoder circuitry with reduced number of inverters and bus lines 失效
标题翻译：具有减少数量的逆变器和总线线路的解码器电路
公开(公告)号：US4758744A
公开(公告)日：1988-07-19
申请号：US935389
申请日：1986-11-26
申请人： Dora Plus
发明人： Dora Plus
IPC分类号： H03M7/22 , H03K19/094
CPC分类号： H03M7/22
摘要： A decoder circuit for fully decoding N input variables includes 2.sup.N logic gates arranged into 2.sup.N-1 pairs of gates, with each gate having N inputs, and one output. The decoder also includes (N-1) inverters for producing the complements of N-1 of the N input variables whereby the (N-1) input variables and their complements are arranged into 2.sup.(N-1) different combinations of (N-1) signals for generating a different combination of (N-1) signals per pair of logic gates. (N-1) inputs of each of the two gates forming a pair of gates are interconnected to receive the same N-1 input signals forming one of the 2.sup.N-1 combinations. The Nth input variable is applied to the Nth input of one gate from each pair of gates and the output of the one gate from each pair is connected to the Nth input of the other gate with which it is paired.
摘要翻译：用于完全解码N个输入变量的解码器电路包括排列成2N-1对门的2N个逻辑门，每个门具有N个输入和一个输出。解码器还包括（N-1）个逆变器，用于产生N个输入变量的N-1的补码，由此将（N-1）个输入变量及其补码排列成（N-1）个不同的组合， 1）用于每对逻辑门产生（N-1）个信号的不同组合的信号。形成一对门的两个门中的每一个的（N-1）个输入被互连以接收形成2N-1组合中的一个的相同的N-1个输入信号。第N个输入变量被施加到每对门的一个门的第N个输入，并且每对门的一个门的输出连接到与其配对的另一个门的第N个输入。

33. 发明授权

US4719461A Method of selective control of electrical circuits and a circuit arrangement for carrying out the method 失效
标题翻译：选择性控制电路的方法和执行该方法的电路装置
公开(公告)号：US4719461A
公开(公告)日：1988-01-12
申请号：US866467
申请日：1986-05-22
申请人： Herbert Keller
发明人： Herbert Keller
IPC分类号： H03K19/173 , H03M7/22 , H04Q1/20 , H04Q1/39
CPC分类号： H03M7/22 , H01L2924/0002
摘要： In an effort to reduce the number of "terminal legs" in highly integrated electronic circuits, two different kinds of coded signals are applied successively to the control terminals thereof, namely: binary coded signals applied in parallel and successive pulses. An evaluation is made only of pulses applied to selected terminals, and a different number of pulses is applied to the individual control terminals. The total number of pulses evaluated is counted in a counter. The counter outputs are decoded in a decoder. The binary coded signals also are decoded in a decoder, and the outputs of both decoders are combined in a selection logic so that both kinds of signals together define a control state. In this manner 3.sup.n different control states are obtained by a number n of control terminals.
摘要翻译：为了减少高度集成的电子电路中的“终端脚”的数量，将两种不同种类的编码信号连续地施加到其控制端，即并行施加的二进制编码信号和连续的脉冲。仅对施加到所选择的端子的脉冲进行评估，并且对各个控制端子施加不同数量的脉冲。评估的总脉冲数在计数器中计数。计数器输出在解码器中解码。二进制编码信号也在解码器中解码，并且两个解码器的输出被组合在选择逻辑中，使得这两种信号一起定义了控制状态。以这种方式，通过n个控制端子获得不同的控制状态。

34. 发明授权

US4697104A Two stage decoder circuit using threshold logic to decode high-order bits and diode-matrix logic to decode low-order bits 失效
标题翻译：使用阈值逻辑解码高阶位和二进制矩阵逻辑以解码低阶位的两级解码器电路
公开(公告)号：US4697104A
公开(公告)日：1987-09-29
申请号：US737464
申请日：1985-05-24
申请人： Yoshinori Okajima
发明人： Yoshinori Okajima
IPC分类号： G11C11/41 , G11C8/10 , G11C11/34 , H01L21/82 , H03M7/22 , H03K19/086 , H03K19/084
CPC分类号： G11C8/10 , H03M7/22
摘要： A two-stage decoder circuit includes a first-stage decoder circuit, for decoding upper bits of an input signal, and a second-stage decoder circuit, which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit which carries out selection or non-selection by comparing the input signal with a predetermined threshold level, and the second-stage decoder circuit is formed by a diode-matrix circuit.
摘要翻译：两级解码器电路包括用于解码输入信号的高位的第一级解码器电路和通过接收第一级解码器电路的所选择的输出信号而激活的第二级解码器电路，并且其解码低位输入信号。第一级解码器电路由通过将输入信号与预定阈值电平进行比较来执行选择或不选择的阈值操作型逻辑电路形成，并且第二级解码器电路由二极管矩阵电路。

35. 发明授权

US4661724A Row decoder 失效
标题翻译：行解码器
公开(公告)号：US4661724A
公开(公告)日：1987-04-28
申请号：US731199
申请日：1985-05-06
申请人： Scott Remington , William L. Martino, Jr.
发明人： Scott Remington , William L. Martino, Jr.
IPC分类号： G11C8/10 , H03M7/22 , H03K19/094 , G11C8/00 , H03K17/16 , H03K19/20
CPC分类号： H03M7/22 , G11C8/10
摘要： A row decoder includes a logic decoder, a word line driver circuit, and first and second coupling circuits. The logic decoder provides a logic high in an inactive cycle and when selected in an active cycle, and a logic low when deselected in the active cycle. Each of a plurality of word line driver circuits receive a decoded address signal which corresponds to that particular driver circuit, each have an output coupled to a corresponding word line, and each have an input which, when at a logic high, causes that word line driver to couple its corresponding decoded address signal to its corresponding word line. The first coupling circuit couples the output of the logic decoder to the input of only the driver circuit which corresponds to an active decoded address signal during the active cycle, and for coupling the output of the logic decoder to all of the driver circuits in the inactive cycle. The second coupling circuit couples the word line which corresponds to the active decoded signal to the output of the logic decoder when the logic decoder is deselected during the active cycle.
摘要翻译：行解码器包括逻辑解码器，字线驱动电路以及第一和第二耦合电路。逻辑解码器在非活动周期中提供逻辑高电平，并在激活周期内选择逻辑电平，当在激活周期中取消选择时，该逻辑电路提供逻辑低电平。多个字线驱动器电路中的每一个接收与该特定驱动器电路相对应的解码的地址信号，每个具有耦合到对应的字线的输出，并且每个具有输入，当逻辑高时，该输入使该字线驱动器将其对应的解码的地址信号耦合到其对应的字线。第一耦合电路将逻辑解码器的输出耦合到仅在激活周期期间对应于有源解码地址信号的驱动器电路的输入，并且将逻辑解码器的输出耦合到不活动的所有驱动器电路周期。当在活动周期期间取消选择逻辑解码器时，第二耦合电路将对应于有效解码信号的字线耦合到逻辑解码器的输出端。

36. 发明授权

US3541547A Code converter 失效
公开(公告)号：US3541547A
公开(公告)日：1970-11-17
申请号：US3541547D
申请日：1968-03-15
申请人： IBM
发明人： ABRAMSON PAUL , JULIUSBURGER HANS Y
IPC分类号： H03M7/00 , H03M7/22 , H03K13/25
CPC分类号： H03M7/22 , H03M7/00

37. 发明授权

US3370288A Decoding circuit 失效
标题翻译：解码电路
公开(公告)号：US3370288A
公开(公告)日：1968-02-20
申请号：US36426164
申请日：1964-05-01
申请人： MARTIN MARIETTA CORP
发明人： WINKLER JOHN T , SMITH EDWIN F JR
IPC分类号： H03K21/08 , H03M7/22
CPC分类号： H03K21/08 , H03M7/22

38. 发明授权

KR1019950001925B1 디코우더 失效
标题翻译：解码器
公开(公告)号：KR1019950001925B1
公开(公告)日：1995-03-06
申请号：KR1019860007914
申请日：1986-09-20
申请人： 지멘스 악티엔게젤샤프트
发明人： 한스페터후흐스 , 위르겐에르.고에츠
IPC分类号： H03M7/22
CPC分类号： H03M7/22 , H03M7/005
摘要： 내용없음.

39. 发明授权

US09124287B1 Scrambler with built in test capabilities for unary DAC 有权
标题翻译：具有一体化DAC的内置测试功能的加扰器
公开(公告)号：US09124287B1
公开(公告)日：2015-09-01
申请号：US14580099
申请日：2014-12-22
申请人： PMC-SIERRA US, INC.
发明人： Stanley Ho , William Michael Lye
IPC分类号： H03M1/10 , H03M1/66 , G01R31/3167 , H03M1/06 , H03M7/02
CPC分类号： G01R31/3167 , H03M1/0673 , H03M1/109 , H03M1/66 , H03M7/02 , H03M7/165 , H03M7/22
摘要： An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs. Each of the N unique scrambling stages is operable to pass signals at the inputs to the outputs in either an unscrambled or scrambled state under control of a control bit provided by an N-bit entropy signal. When an N+1 bit input signal is applied to the scrambler inputs and the N-bit entropy signal is randomized the analog output signal from the DAC has improved linearity compared to the analog output signal generated from a non-scrambled input, and when a test input signal is applied to the scrambler inputs and the entropy signal is swept through 2N orthogonal values the analog output signal from the DAC indicates whether a fault exists in one of the scrambler and the DAC.
摘要翻译：一种包括具有多个加扰器输入和2N个加扰器输出的加扰器的装置，以及连接到加扰器的一次加密数模转换器（DAC），以基于2N个加扰器输出产生模拟输出信号。加扰器具有N个唯一的加扰阶段，其按扰频器输入和从第一加扰阶段到最后加扰阶段的加扰器输出之间的顺序排列。 N个唯一加扰阶段中的每一个具有多个级输入和输出，其中第一加扰级的级输入连接到加扰器输入，除了与第一加扰级相连的第一加扰级之外的每个加扰级的级输出下一个加扰阶段，以及连接到加扰器输出的最后一个加扰级的级输出。 N个唯一加扰级中的每一个可操作以在由N位熵信号提供的控制位的控制下以未加扰或加扰状态将输入处的信号传递到输出。当将N + 1位输入信号施加到扰频器输入并且N位熵信号被随机化时，与从非加扰输入产生的模拟输出信号相比，来自DAC的模拟输出信号具有改善的线性度，并且当测试输入信号被施加到加扰器输入，并且熵信号通过2N个正交值扫描，来自DAC的模拟输出信号指示在扰频器和DAC之一中是否存在故障。

40. 发明授权

US06919836B2 High speed encoder for high speed analog-to-digital converter 有权
标题翻译：用于高速模数转换器的高速编码器
公开(公告)号：US06919836B2
公开(公告)日：2005-07-19
申请号：US10436318
申请日：2003-05-12
申请人： Ho-young Lee
发明人： Ho-young Lee
IPC分类号： H03M1/12 , H03M7/16 , H03M7/22 , H03M1/36
CPC分类号： H03M7/22 , H03M7/165
摘要： A binary encoder which has a fast conversion speed, occupies a small area, and consumes a small amount of power is provided. The binary encoder includes first and second latch transistors, first and second charge transistors, first and second control transistors, first and second discharge transistors, and first and second inverters. The first charge transistor charges a first output node to a level of a power voltage in response to a clock signal. The second charge transistor charges a second output node to the level of the power voltage in response to the clock signal. The first discharge transistor discharges a first control node to a level of a ground voltage in response to a first input signal. The second discharge transistor discharges a second control node to the level of the ground voltage in response to a second input signal.
摘要翻译：具有快速转换速度的二进制编码器占用小面积，并且消耗少量的功率。二进制编码器包括第一和第二锁存晶体管，第一和第二充电晶体管，第一和第二控制晶体管，第一和第二放电晶体管以及第一和第二反相器。第一充电晶体管响应于时钟信号将第一输出节点充电到电源电压的电平。第二充电晶体管响应于时钟信号而将第二输出节点充电到电源电压的电平。第一放电晶体管响应于第一输入信号将第一控制节点放电至接地电压的电平。第二放电晶体管响应于第二输入信号将第二控制节点放电到接地电压的电平。

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