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31. 发明申请

WO1994027363A1 CIRCUITRY FOR AMPLIFIER 审中-公开
标题翻译：放大器电路
公开(公告)号：WO1994027363A1
公开(公告)日：1994-11-24
申请号：PCT/DE1994000569
申请日：1994-05-12
申请人： TELENORMA GMBH , OEHM, Jürgen
发明人： TELENORMA GMBH
IPC分类号： H03F03/45
CPC分类号： H03F3/45659 , H03F3/45179 , H03F3/45183 , H03F3/45197 , H03F2203/45658
摘要： Two differential voltage-controlled current sources are applied on a substrate by CMOS technology. Each current source has an inverting and a non-inverting input. One current source is designed as an input element (E) and the other current source is designed as a load element (L). The output of the current source designed as an input element (E) and the output of the current source designed as a load element (L) are connected to each other and to a device (A) for calculating the arithmetic difference between both output currents. The output of the device (A) is connected to an input of the load element (L), causing a negative feedback. With this circuitry, an amplifier may be produced which, when properly designed, is characterised by high linearity.
摘要翻译：通过差分电压控制的两个电流源通过CMOS技术被施加到衬底。每个电流源都有一个反相输入和一个非反相输入。一个电流源是输入元件（E），另一个电流源是负载元件（L）。构成输入元件（E）的电流源的输出和构成充电元件（L）的电流源的输出彼此连接并连接到装置（ A）计算两个输出电流之间的算术差。装置（A）的输出连接到充电元件（L）的输入端，以引起反耦合现象。这种配置因此使得可以通过CMOS技术产生放大器，该放大器在适当设计时具有高线性特征。

32. 发明申请

WO1980001747A1 SEMICONDUCTOR DIFFERENTIAL AMPLIFIER HAVING FEEDBACK BIAS CONTROL FOR STABILIZATION 审中-公开
标题翻译：具有反馈偏置控制用于稳定的半导体差分放大器
公开(公告)号：WO1980001747A1
公开(公告)日：1980-08-21
申请号：PCT/US1980000087
申请日：1980-01-30
申请人： WESTERN ELECTRIC CO INC
发明人： WESTERN ELECTRIC CO INC , TSIVIDIS Y
IPC分类号： H03F03/45
CPC分类号： H03F3/45708 , H03F3/45183 , H03F2203/45508 , H03F2203/45658
摘要： An MOS differential amplifier includes a pair of substantially identical branches, each branch having a signal input MOS transistor (M1, M3) feeding a separate MOS load transistor (M5, M7). Both branches are supplied current by a single current-source MOS transistor (M10). In order to stabilize the (source-to-drain) bias voltages of the signal input and load transistors against fluctuations caused by semiconductor wafer-to-wafer processing variations, an auxiliary amplifier branch (M2, M4) is added (for sensing the bias voltage) together with a feedback loop (M8) to the current-source (for controlling the current in response to the sensing of the bias voltage).

33. 发明申请

WO02087462A9 INTEGRATED LOW-CORNER FREQUENCY HIGH PASS FILTER CIRCUIT 审中-公开
标题翻译：集成的低频高通滤波器电路
公开(公告)号：WO02087462A9
公开(公告)日：2003-02-06
申请号：PCT/EP0204337
申请日：2002-04-19
申请人： EM MICROELECTRONIC MARIN SA
发明人： BUESCHER KEVIN SCOTT , LAUFFENBURGER JAMES HAROLD
IPC分类号： H03F3/45 , H03H11/12 , A61C17/20 , A61C1/07 , A61C1/14 , B06B3/00
CPC分类号： H03H11/126 , H03F3/45183 , H03F2203/45318 , H03F2203/45371 , H03F2203/45462 , H03F2203/45646 , H03F2203/45658
摘要： There is described a low-corner frequency high pass filter circuit comprising: an operational amplifier (12) having an inverting input (14), a non-inverting input (24) and an ouput (22), a series capacitor (26) having a first end connected to the non-inverting input (24) of the operational amplifier (12) and a second end connected to an input signal (Vin, 28), a first resistor (16) having a first end connected to the inverting input (14) of the operational amplifier (12) and a second end connected to a reference potential, a feedback resistor (20) having a first end connected to the inverting input (14) of the operational amplifier (12) and a second end connected to the output (22) of the differential amplifier (12), and a low gain amplifier circuit (30) having a first input connected to the reference voltage, a second input connected to the output (22) of the operational amplifier (12) and an output (32) connected to the non-inverting input (24) of the operational amplifier (12).
摘要翻译：描述了一种低转角频率高通滤波器电路，包括：具有反相输入端（14），非反相输入端（24）和输出端（22）的运算放大器（12）;串联电容器（26）第一端连接到运算放大器（12）的非反相输入端（24），第二端连接到输入信号（Vin，28）;第一电阻器（16），其第一端连接到反相输入端（12）的反相输入端（14）的第一端和连接到参考电位的第二端;反馈电阻器（20），其具有连接到运算放大器（12）的反相输入端（14）的第一端和连接到运算放大器到差分放大器（12）的输出端（22）;以及低增益放大器电路（30），具有连接到参考电压的第一输入端，连接到运算放大器（12）的输出端（22）的第二输入端，和连接到运算放大器（12）的非反相输入端（24）的输出端（32）。

34. 发明申请

WO2002097974A2 ACTIVE AUTO ZERO CIRCUIT FOR TIME CONTINUOUS OPEN LOOP AMPLIFIERS 审中-公开
标题翻译：用于时间连续开环放大器的主动自动零电路
公开(公告)号：WO2002097974A2
公开(公告)日：2002-12-05
申请号：PCT/US2002/016631
申请日：2002-05-24
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： BLON, Thomas , CYRUSIAN, Sasan
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/45659 , H03F3/45753 , H03F2203/45418 , H03F2203/45424 , H03F2203/45431 , H03F2203/45616 , H03F2203/45658
摘要： An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the second phase, the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled.
摘要翻译：公开了一种用于开环差分放大器的有源偏移消除电路。放大器工作在两相时钟，第一相出现正常工作，第二相发生偏移检测和取消。在第二阶段，当两个差分输入连接到公共源时，偏移消除电路测量由放大器产生的偏移。该电路然后调整偏置电流并存储该调整以在放大器的操作阶段消除偏移。在运行阶段，在时钟的第一阶段，存储的调整用于偏置放大器的两个输入级之一中的电流，从而抵消由放大器电路赋予的任何偏移。一个每个时钟周期，任何额外的偏移量也被类似地检测和取消。

35. 发明申请

WO02071601A2 PREAMPLIFIER CIRCUIT FOR A PHOTODETECTOR 审中-公开
标题翻译：用于照相机的前置放大器电路
公开(公告)号：WO02071601A2
公开(公告)日：2002-09-12
申请号：PCT/EP0201331
申请日：2002-02-04
申请人： EM MICROELECTRONIC MARIN SA
发明人： BUESCHER KEVIN SCOTT , LAUFFENBURGER JAMES HAROLD , ARACHTINGI JOHN WILLIAM
IPC分类号： H03F3/30 , H03F3/45 , H03G1/00 , H03G
CPC分类号： H03G1/0088 , H03F3/3023 , H03F3/45183 , H03F2203/30054 , H03F2203/30151 , H03F2203/30156 , H03F2203/45651 , H03F2203/45658 , H03F2203/7236 , H03G1/0023
摘要： An amplifier circuit (20) for a photodetector includes a transconductance variable gain stage (32). The transconductance variable gain stage (32) has an input (34) capable of connecting to the photedetector and an output (40). A transconductance gain stage (44) has an input (42) connected to the output (40) of the transconductance variable gain stage (32). A feedback resistor (46) is connected between an output (48) of the transconductance gain stage (44) and the input (42) of the transconductance gain stage (44).
摘要翻译：用于光电检测器的放大器电路（20）包括跨导可变增益级（32）。跨导可变增益级（32）具有能够连接到光电检测器的输入端（34）和输出端（40）。跨导增益级（44）具有连接到跨导可变增益级（32）的输出（40）的输入（42）。反馈电阻（46）连接在跨导增益级（44）的输出（48）和跨导增益级（44）的输入端（42）之间。

36. 发明申请

WO00002310A1 IMPROVED EXPONENTIAL CURRENT GENERATOR AND METHOD 审中-公开
标题翻译：改进的指导性电流发生器和方法
公开(公告)号：WO00002310A1
公开(公告)日：2000-01-13
申请号：PCT/US1999/014695
申请日：1999-06-30
IPC分类号： G06G7/24 , H03F3/45 , H03G1/00 , H03G3/02
CPC分类号： H03F3/45179 , H03F3/45085 , H03F2203/45454 , H03F2203/45471 , H03F2203/45658 , H03G1/0023
摘要： An apparatus and method of generating a current pair Ip, Im where the ratio of the pair is exponentially related to a control signal, and where either Ip or Im is greater than or less than a minimum or maximum value. The apparatus includes a feedback correction circuit used to sense the value of Im or Ip. The correction circuit supplies a boost current Iboost when the sensed value of Ip or Im is less than or greater than the minimum or maximum value. Iboost is preferably maintained proportional to the difference of the desired value and Ip or Im.
摘要翻译：产生电流对Ip，Im的装置和方法，其中该对的比率与控制信号成指数关系，并且其中Ip或Im大于或小于最小值或最小值。该装置包括用于感测Im或Ip的值的反馈校正电路。当Ip或Im的感测值小于或大于最小值或最大值时，校正电路提供升压电流Iboost。 Iboost优选地与期望值和Ip或Im的差成比例。

37. 发明申请

WO1998000911A1 DIFFERENTIAL AMPLIFIER 审中-公开
标题翻译：差分放大器
公开(公告)号：WO1998000911A1
公开(公告)日：1998-01-08
申请号：PCT/GB1997001754
申请日：1997-06-26
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , GASPARIK, Frank
IPC分类号： H03F03/45
CPC分类号： H03F3/4521 , H03F3/3028 , H03F2203/45508 , H03F2203/45656 , H03F2203/45658
摘要： The invention provides for a receiver, such as a differential receiver (300), that includes a first input (302), a second input (304), and an output (306). The receiver (300) has a first signal path from the first input (302) to the output, the first signal path including a first differential amplifier (308) and a first active load (312) wherein the first differential amplifier (308) has an end connected to a first power supply voltage (VDD) and a second end connected to a second power supply voltage and the first active load (312). The first differential amplifier (308) also has a connection to the first input (302) and the second input (304), and the first active load (312) has a connection to the output (306). The receiver (300) also has a second signal path from the second input (304) to the output (306), the second signal path including a second differential amplifier (310) and second active load (314), wherein the second differential amplifier (310) has an end connected to a first power supply voltage and a second end connected to a second power supply voltage (VDD) and the second active load (314). The second differential amplifier (310) also has a connection to the first input (300) and the second input (304), and the second active load (314) has a connection to the output (306). The first signal path and the second signal path both have the same number of devices.
摘要翻译：本发明提供了一种包括第一输入（302），第二输入（304）和输出（306）的接收器，例如差分接收器（300）。接收器（300）具有从第一输入（302）到输出的第一信号路径，第一信号路径包括第一差分放大器（308）和第一有效负载（312），其中第一差分放大器（308）具有连接到第一电源电压（VDD）的端部和连接到第二电源电压的第二端和第一有效负载（312）。第一差分放大器（308）还具有与第一输入（302）和第二输入（304）的连接，并且第一有效负载（312）具有到输出（306）的连接。接收机（300）还具有从第二输入（304）到输出（306）的第二信号路径，第二信号路径包括第二差分放大器（310）和第二有源负载（314），其中第二差分放大器（310）具有连接到第一电源电压的端部和连接到第二电源电压（VDD）和第二有源负载（314）的第二端。第二差分放大器（310）还具有与第一输入（300）和第二输入（304）的连接，并且第二有效负载（314）具有到输出端（306）的连接。第一信号路径和第二信号路径都具有相同数量的设备。

38. 发明公开

KR1020040010345A 반도체 집적 회로 장치 有权
标题翻译：半导体集成电路设备
公开(公告)号：KR1020040010345A
公开(公告)日：2004-01-31
申请号：KR1020030050466
申请日：2003-07-23
申请人： 후지쯔 가부시끼가이샤
发明人： 이시다히데키 , 오노메구미
IPC分类号： H03K19/00
CPC分类号： G05F3/262 , H03F3/345 , H03F3/4521 , H03F2203/45658 , H03F2203/45702
摘要： PURPOSE: To provide a semiconductor integrated circuit device capable of generating a stable constant current even at low power supply voltage. CONSTITUTION: The semiconductor integrated circuit device having a 1st conductive type 1st MIS transistor 3, a 2nd conductive type 2nd MIS transistor 8 and a resistor 9 which are connected in series between a 1st power supply line Vdd and a 2nd power supply line Vss is provided with a 3rd MIS transistor 4 whose gate is connected to a connection node N4 between the 1st MIS transistor 3 and the 2nd MIS transistor 8 and whose drain is connected to a connection node N1 between the 2nd MIS transistor 8 and the resistor 9.
摘要翻译：目的：提供即使在低电源电压下能够产生稳定恒定电流的半导体集成电路器件。具体实施方式提供具有串联在第一电源线Vdd和第二电源线Vss之间的第一导电类型的第一MIS晶体管3，第二导电型第二MIS晶体管8和电阻器9的半导体集成电路器件具有第三MIS晶体管4，其栅极连接到第一MIS晶体管3和第二MIS晶体管8之间的连接节点N4，并且其漏极连接到第二MIS晶体管8和电阻器9之间的连接节点N1。

39. 发明授权

KR100163783B1 출력단에서 소모되는 동작 전류가 일정한 연산 증폭기 회로 失效
标题翻译：运算放大器电路的输出电流
公开(公告)号：KR100163783B1
公开(公告)日：1999-03-20
申请号：KR1019960001796
申请日：1996-01-27
申请人： 닛뽕덴끼 가부시끼가이샤
发明人： 가또후미히꼬
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F3/3008 , H03F3/3023 , H03F3/3027 , H03F3/45112 , H03F3/45179 , H03F3/4521 , H03F2203/45091 , H03F2203/45188 , H03F2203/45658 , H03F2203/45676
摘要： 입력단(10)과 오차 보정 레벨 시프트단(20)과 출력단(30)이 조합되어 연산 증폭기 회로를 형성하며, 오차 보정 레벨 시프트단은 전류 미러 회로(MR13)의 입력 노드(CN5)와 연결된 인버팅 트랜지스터(MN5)를 포함하며, 입력단의 출력 전위 레벨에 응답하여 전류 미러 회로의 출력 노드(OUT11)에 연결된 정전류원(112)과 전류 미러 회로의 출력 전위 전압을 제어하며, 출력 노드(OUT11)의 출력 전위레벨이 인버팅 트랜지스터의 채널 도우핑 레벨의 변화에 영향받지 않도록 한다.

40. 发明授权

EP2562936B1 Differential integrated input circuit 有权
公开(公告)号：EP2562936B1
公开(公告)日：2018-09-12
申请号：EP12177426.9
申请日：2012-07-23
申请人： NXP B.V.
发明人： Waardenburg, Cornelis Klaas , Butselaar, Stefan Gerhard Erich , Gelissen, Ben , El-Ghorba, Mehdi , Boomkamp, Louk
IPC分类号： H03K5/24 , H03F3/45
CPC分类号： H03F3/4508 , H03F3/45179 , H03F2203/45306 , H03F2203/45318 , H03F2203/45352 , H03F2203/45374 , H03F2203/45394 , H03F2203/45562 , H03F2203/45594 , H03F2203/45604 , H03F2203/45658 , H03F2203/45702 , H03K5/2418 , H03K5/2481
摘要： An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.

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