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1. 发明申请

WO1998000789A1 INTER-BUS BRIDGE CIRCUIT 审中-公开
标题翻译：交叉车桥电路
公开(公告)号：WO1998000789A1
公开(公告)日：1998-01-08
申请号：PCT/GB1997001616
申请日：1997-06-16
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , RYMPH, Alan, D. , CORRIGAN, Brian, E., III
IPC分类号： G06F13/40
CPC分类号： G06F12/0866 , G06F12/0879 , G06F13/4059
摘要： The present invention provides for a bus bridge circuit (206) having a memory port (4) integrated therewith for upstream memory access independent of the activity on a primary bus (252) connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port (4) to a PCI bridge circuit (206) usable for upstream data transfers to an attached cache memory subsystem. The memory port (4) of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port (4) of the present invention utilizes FIFO devices (310) to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port (4) allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus (252), while minimizing the performance impact on a secondary bus (256).
摘要翻译：本发明提供一种具有与其集成的存储器端口（4）的总线桥式电路（206），用于独立于连接到桥式电路的主总线（252）上的活动的上游存储器访问。在优选实施例中，本发明将可用于向连接的高速缓存存储器子系统的上游数据传输的PCI桥接电路（206）添加存储器端口（4）。本发明的存储器端口（4）优选地是64位宽，以允许高速数据访问共享高速缓冲存储器子系统。本发明的替代实施例实现了一个128位宽的数据通路，连接到高速缓存存储器子系统。本发明的存储器端口（4）利用FIFO设备（310）来隔离存储器端口事务与次级总线事务。存储器端口（4）的FIFO设计允许高速传输突发到共享存储器，而与主总线（252）上的活动无关，同时最小化对次级总线（256）的性能影响。

2. 发明申请

WO1997007455A2 DATA STORAGE APPARATUS 审中-公开
标题翻译：数据存储设备
公开(公告)号：WO1997007455A2
公开(公告)日：1997-02-27
申请号：PCT/GB1996001837
申请日：1996-07-30
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , DULAC, Keith, Bernard , PHILLIPS, Grover, George
IPC分类号： G06F11/00
CPC分类号： G06F11/201 , G06F11/1076 , G06F2201/85 , G06F2211/1014 , H04N7/17336
摘要： The invention provides for a data storage apparatus including a first bus (104), a second bus (106), and a storage module (102) having a first and second output with the first output being connected to the first bus (104) and a second output being connected to the second bus (106). A first buffer storage (108) is connected to the first bus (104), and a second buffer storage (110) is connected to the second bus (106). The second buffer storage (110) includes an error correction module (110c), and first and second network adapters (112, 114) are connected to the first (104) and second (106) buses, respectively. The first network adapter (112) also includes a connection to the first buffer (108). A processor (120) in the apparatus includes a first processor means for transferring the data using a first path through the first output in the storage module (102) to the first buffer storage (108) and from the first buffer storage (108) to the first network adapter (112). A second processor means (120) is provided for transferring data using a second path through the second output to the second buffer storage (110) through the error correction module (110c) and from the second buffer storage (110) to the second network adapter (114), wherein the second processor means is responsive to an error in the storage module (102).
摘要翻译：本发明提供了一种包括第一总线（104），第二总线（106）和存储模块（102）的数据存储装置，该存储模块具有第一和第二输出，第一输出端连接到第一总线（104），第第二输出端连接到第二总线（106）。第一缓冲存储器（108）连接到第一总线（104），第二缓冲存储器（110）连接到第二总线（106）。第二缓冲存储器（110）包括错误校正模块（110c），并且第一和第二网络适配器（112,114）分别连接到第一（104）和第二（106）总线。第一网络适配器（112）还包括到第一缓冲器（108）的连接。装置中的处理器（120）包括第一处理器装置，用于使用通过存储模块（102）中的第一输出的第一路径将数据传送到第一缓冲存储器（108），并且从第一缓冲存储器（108）到第一网络适配器（112）。提供第二处理器装置（120），用于使用通过第二输出的第二路径通过错误校正模块（110c）将数据传送到第二缓冲存储器（110），并且从第二缓冲存储器（110）传送到第二网络适配器（114），其中所述第二处理器装置响应于所述存储模块（102）中的错误。

3. 发明申请

WO1997038369A1 BUS PERFORMANCE MONITORING APPARATUS AND METHOD 审中-公开
标题翻译：总线性能监测装置和方法
公开(公告)号：WO1997038369A1
公开(公告)日：1997-10-16
申请号：PCT/GB1997000968
申请日：1997-04-07
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , McCOMBS, Craig, C.
IPC分类号： G06F11/34
CPC分类号： G06F11/349 , G06F11/3409 , G06F2201/87 , G06F2201/88
摘要： The invention provides for a method and apparatus for measuring performance of an I/O bus (20). The method includes the steps of (a) determining a number of I/O bus clock cycles that occur during I/O bus transactions involving a peripheral device during a time period, and (b) determining a bus performance value for the I/O bus based on the number of I/O bus clock cycles determined in step (a). One embodiment of the apparatus includes a mechanism for determining a bus utilization value for the I/O bus based on the number of I/O bus clock cycles counted by the counter, while another embodiment of the apparatus includes a mechanism for determining a bus efficiency value for the I/O bus based on the number of I/O bus clock cycles counted by the counter.
摘要翻译：本发明提供了一种用于测量I / O总线（20）的性能的方法和装置。该方法包括以下步骤：（a）确定在一段时间内涉及外围设备的I / O总线事务期间发生的I / O总线时钟周期数，以及（b）确定I / O总线性能值总线基于在步骤（a）中确定的I / O总线时钟周期的数量。该装置的一个实施例包括一种用于基于由计数器计数的I / O总线时钟周期数来确定I / O总线的总线利用值的机制，而该装置的另一实施例包括用于确定总线效率的机构根据计数器计数的I / O总线时钟周期数，I / O总线的值。

4. 发明申请

WO1997036326A1 INTEGRATED CIRCUIT PROTECTION DEVICE AND METHOD 审中-公开
标题翻译：集成电路保护装置及方法
公开(公告)号：WO1997036326A1
公开(公告)日：1997-10-02
申请号：PCT/GB1997000951
申请日：1997-03-26
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , COLE, Richard, K. , YAKURA, James, P.
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , G06F21/75 , G06F21/87 , G11C7/24 , H01L2924/0002 , Y10S257/901 , Y10S257/906 , Y10S257/908 , H01L2924/00
摘要： The present invention provides for an integrated circuit chip (100) having one or more circuit elements (102) that perform a desired circuit function with the circuit elements being encompassed by a molding compound (108) that forms a package for the chip. The molding compound has a capacitance associated with it and the integrated circuit chip (100) includes a second integrated circuit element (104) within the molding compound (108) and which second integrated circuit element monitors the molding compound (108) to detect a change in capacitance in the molding compound (108) resulting from a removal of a portion or all of the molding compound (108). In response to a detection of a change in the capacitance, the second integrated circuit element (102) alters the desired circuit function provided by the other integrated circuit elements.
摘要翻译：本发明提供一种具有一个或多个电路元件（102）的集成电路芯片（100），该电路元件（102）执行期望的电路功能，其中电路元件被形成用于芯片的封装的模制化合物（108）包围。模制化合物具有与其相关联的电容，并且集成电路芯片（100）在模制化合物（108）内包括第二集成电路元件（104），并且第二集成电路元件监测模制化合物（108）以检测变化在由模制化合物（108）中除去部分或全部模塑料（108）而产生的静电容量。响应于电容变化的检测，第二集成电路元件（102）改变由其它集成电路元件提供的期望的电路功能。

5. 发明申请

WO1997033410A1 SERIAL DATA INTERFACE METHOD AND APPARATUS 审中-公开
标题翻译：串行数据接口方法和设备
公开(公告)号：WO1997033410A1
公开(公告)日：1997-09-12
申请号：PCT/GB1997000527
申请日：1997-02-24
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , ELLIS, Jackson, L.
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： The invention provides for a serial data interface device (30) which is coupled to electronic devices or other data transmitters or receivers, such as disk, optical, tape or CD-ROM drives, computers, printers etc. The interface (30) includes first (32) and second (34) ports capable of receiving and transmitting information to respective electronic devices, and first (50) and second (60) storage devices, such as frame buffers, for storing information. Each of the storage devices is coupled to both the first (32) and second (34) ports and are coupled to another electronic device. Included in each storage device (50, 60) is a main memory (92) that is coupled to at least one of the 100 electronic devices and at least one of the ports (32, 34). Further included is a buffer allocation control (102) that is coupled to the at least one electronic device and at least one of the ports (32, 34).
摘要翻译：本发明提供一种串行数据接口设备（30），其耦合到诸如磁盘，光学，磁带或CD-ROM驱动器，计算机，打印机等的电子设备或其他数据发射器或接收器。接口（30）包括第一（32）和第二（34）端口，能够接收和发送信息到各个电子设备，以及第一（50）和第二（60）个存储设备，例如帧缓冲器，用于存储信息。每个存储设备耦合到第一（32）端口和第二端口（34）两端并且耦合到另一个电子设备。包括在每个存储设备（50,60）中的是主存储器（92），其耦合到100个电子设备和至少一个端口（32,34）中的至少一个。进一步包括耦合到至少一个电子设备和至少一个端口（32,34）的缓冲器分配控制（102）。

6. 发明申请

WO1998000916A1 CIRCUIT AND METHOD FOR REDUCING THE EFFECTS OF METASTABILITY 审中-公开
标题翻译：降低可渗透性影响的电路和方法
公开(公告)号：WO1998000916A1
公开(公告)日：1998-01-08
申请号：PCT/GB1997001611
申请日：1997-06-16
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , NGUYEN, Hoang , SCHULTZ, Richard, T.
IPC分类号： H03K03/037
CPC分类号： H03K3/0375
摘要： The invention provides for a meta-hardened circuit (100) that reduces the effects of metastability and includes a pulse generator (110) coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer (140), preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device (160), such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator (110) preferably includes a combining device (120) and a delay device (112). The buffer (140) preferably includes at least one tri-state inverter (144) and a keeper circuit (145). A method to reduce the metastability effects is also provided and includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.
摘要翻译：本发明提供了减少亚稳态影响的元硬化电路（100），并且包括被连接以接收第一时钟信号并响应于此产生第二时钟信号和使能信号的脉冲发生器（110）。耦合优选三态的缓冲器（140），以接收第一数据信号和使能信号，并响应于此产生第二数据信号。诸如触发器的双稳态器件（160）被耦合以接收第二时钟信号和第二数据信号。脉冲发生器（110）优选地包括组合装置（120）和延迟装置（112）。缓冲器（140）优选地包括至少一个三态反相器（144）和保持器电路（145）。还提供了一种降低亚稳效应的方法，包括产生第二数据输入信号和第二时钟信号之间的延迟的步骤，该延迟大于第一数据输入信号和第一时钟信号之间的延迟。优选的发生步骤在一个时钟周期内发生。该方法还优选地包括通过响应于第一时钟信号产生第二时钟信号并组合第一和第二时钟信号以产生使能信号来产生使能脉冲，以及响应于第一数据输入产生第二数据输入信号信号，其中产生所述第二数据输入信号包括接收使能信号。该方法优选地包括响应于第二数据输入信号和第二时钟信号产生输出信号的步骤，输出信号具有降低的亚稳效应。

7. 发明申请

WO1998000911A1 DIFFERENTIAL AMPLIFIER 审中-公开
标题翻译：差分放大器
公开(公告)号：WO1998000911A1
公开(公告)日：1998-01-08
申请号：PCT/GB1997001754
申请日：1997-06-26
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , GASPARIK, Frank
IPC分类号： H03F03/45
CPC分类号： H03F3/4521 , H03F3/3028 , H03F2203/45508 , H03F2203/45656 , H03F2203/45658
摘要： The invention provides for a receiver, such as a differential receiver (300), that includes a first input (302), a second input (304), and an output (306). The receiver (300) has a first signal path from the first input (302) to the output, the first signal path including a first differential amplifier (308) and a first active load (312) wherein the first differential amplifier (308) has an end connected to a first power supply voltage (VDD) and a second end connected to a second power supply voltage and the first active load (312). The first differential amplifier (308) also has a connection to the first input (302) and the second input (304), and the first active load (312) has a connection to the output (306). The receiver (300) also has a second signal path from the second input (304) to the output (306), the second signal path including a second differential amplifier (310) and second active load (314), wherein the second differential amplifier (310) has an end connected to a first power supply voltage and a second end connected to a second power supply voltage (VDD) and the second active load (314). The second differential amplifier (310) also has a connection to the first input (300) and the second input (304), and the second active load (314) has a connection to the output (306). The first signal path and the second signal path both have the same number of devices.
摘要翻译：本发明提供了一种包括第一输入（302），第二输入（304）和输出（306）的接收器，例如差分接收器（300）。接收器（300）具有从第一输入（302）到输出的第一信号路径，第一信号路径包括第一差分放大器（308）和第一有效负载（312），其中第一差分放大器（308）具有连接到第一电源电压（VDD）的端部和连接到第二电源电压的第二端和第一有效负载（312）。第一差分放大器（308）还具有与第一输入（302）和第二输入（304）的连接，并且第一有效负载（312）具有到输出（306）的连接。接收机（300）还具有从第二输入（304）到输出（306）的第二信号路径，第二信号路径包括第二差分放大器（310）和第二有源负载（314），其中第二差分放大器（310）具有连接到第一电源电压的端部和连接到第二电源电压（VDD）和第二有源负载（314）的第二端。第二差分放大器（310）还具有与第一输入（300）和第二输入（304）的连接，并且第二有效负载（314）具有到输出端（306）的连接。第一信号路径和第二信号路径都具有相同数量的设备。

8. 发明申请

WO1997050026A1 APPARATUS AND METHOD FOR GENERATING A CURRENT WITH A POSITIVE TEMPERATURE COEFFICIENT 审中-公开
标题翻译：用于产生具有正温度系数的电流的装置和方法
公开(公告)号：WO1997050026A1
公开(公告)日：1997-12-31
申请号：PCT/GB1997001687
申请日：1997-06-23
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , GASPARIK, Frank
IPC分类号： G05F03/26
CPC分类号： G05F3/267
摘要： The invention provides for a bias current generator (10) which includes a first circuit component (MP2) having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component (Q2) having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator (10) includes an impedance element (R2) connected to the first circuit component (MP2) and the second component (Q2), the impedance element (R2) having (i) an impedance which increases as an operating temperature of the impedance element increases, and (ii) a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current. Moreover, the bias current generator (10) includes a mirroring circuit (MP3, MP4) for generating a second current which mirrors the first current flowing through the impedance element (R2). A method for generating a bias current that counteracts the effects temperature has upon electron and hole mobility is also disclosed.
摘要翻译：本发明提供一种偏置电流发生器（10），该偏置电流发生器（10）包括第一电路部件（MP2），该第一电路部件具有在其一对端子上产生的第一电压，第一电压随第一电路部件的工作温度而降低。偏置电流发生器还包括具有在其一对端子上产生的第二电压的第二电路部件（Q2），当第二电路部件的工作温度升高时，第二电压降低。此外，偏置电流发生器（10）包括连接到第一电路部件（MP2）和第二部件（Q2）的阻抗元件（R2），阻抗元件（R2）具有（i）阻抗元件的工作温度上升，并且（ii）流过其中的第一电流，其中第一电压的降低导致第一电流的相应增加，并且第二电压的降低导致第一电流的相应增加。此外，偏置电流发生器（10）包括用于产生第二电流的镜像电路（MP3，MP4），其反射流过阻抗元件（R2）的第一电流。还公开了一种用于产生抵消效应温度的偏置电流对电子和空穴迁移率的方法。

9. 发明申请

WO1998006540A1 APPARATUS AND METHOD FOR POLISHING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：抛光半导体器件的装置和方法
公开(公告)号：WO1998006540A1
公开(公告)日：1998-02-19
申请号：PCT/GB1997001894
申请日：1997-07-15
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , ALLMAN, Derryl, D., J. , GREGORY, John, W.
IPC分类号： B24B37/04
CPC分类号： B24B53/017 , B24B1/04 , Y10S451/91
摘要： The present invention provides for a method and apparatus for conditioning a polishing pad (202) in a semiconductor polishing arrangement (200) in which slurry (216) is directed under pressure at the polishing pad (202) and by means of a slurry spray dispenser (210, 214). Additionally, energy, such as ultrasonic energy, may be added (404) to the slurry as it is directed towards the polishing pad (202), wherein embedded material in the polishing pad (202) is removed or dislodged.
摘要翻译：本发明提供一种用于调节半导体抛光装置（200）中的抛光垫（202）的方法和装置，其中浆料（216）在抛光垫（202）处被压力地定向并且通过浆料喷射分配器（210,214）。此外，当浆料被引导到抛光垫（202）时，诸如超声波能量的能量（404）可被添加到浆料中，其中抛光垫（202）中的嵌入材料被去除或移动。

10. 发明申请

WO1998000872A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：集成电路装置及其制造方法
公开(公告)号：WO1998000872A1
公开(公告)日：1998-01-08
申请号：PCT/GB1997001699
申请日：1997-06-25
申请人： SYMBIOS LOGIC INC. , GILL, David, Alan
发明人： SYMBIOS LOGIC INC. , GILL, David, Alan , SELISKAR, John, J. , ALLMAN, Derryl, D., J. , GREGORY, John, W. , YAKURA, James, P. , KWONG, Dim, Lee
IPC分类号： H01L29/92
CPC分类号： H01L28/40 , H01L27/0688 , H01L29/42324
摘要： The present invention relates to a semiconductor device, preferably a capacitor (12), and a method of forming the same. The method adds only a single additional masking step to the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer (70) is formed over a bottom electrode (18). An opening (72) having a sidewall (72A) etched in the insulation layer (70) using a mask (52) to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer (74) and conductive layer (76) are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer (74) so that the conductive layer (76) and dielectric layer (74) remaining forms, for example, the top electrode (24) and dielectric layer (20) of the integrated circuit capacitor. The top electrode (24) is thus disposed above a central region (20A) which remains of the dielectric layer (20) and between a peripheral region which remains of the dielectric layer (20).
摘要翻译：本发明涉及半导体器件，优选电容器（12）及其形成方法。该方法在制造过程中仅添加一个附加的掩模步骤，并且减少了与各种层的对准有关的问题。在底部电极（18）上形成相对较厚的绝缘层（70）。具有使用掩模（52）在绝缘层（70）中蚀刻以暴露底部电极的一部分的侧壁（72A）的开口（72）。一旦去除了掩模，然后在包括侧壁的整个结构上顺序地沉积介电层（74）和导电层（76）。此后，使用化学机械抛光来去除导电层和电介质层（74）的部分，使得残留的导电层（76）和电介质层（74）形成例如顶部电极（24）和电介质集成电路电容器的层（20）。因此，顶部电极（24）设置在电介质层（20）的保留的中心区域（20A）的上方，并且位于介质层（20）的保留的外围区域之间。

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