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31. 发明申请

WO2009050703A2 DATA STORAGE IN ANALOG MEMORY CELL ARRAYS HAVING ERASE FAILURES 审中-公开
标题翻译：数据存储在具有擦除故障的模拟存储器单元阵列中
公开(公告)号：WO2009050703A2
公开(公告)日：2009-04-23
申请号：PCT/IL2008/001356
申请日：2008-10-12
申请人： ANOBIT TECHNOLOGIES , SHALVI, Ofir , WINTER, Shai , SOMMER, Naftali , SOKOLOV, Dotan
发明人： SHALVI, Ofir , WINTER, Shai , SOMMER, Naftali , SOKOLOV, Dotan
IPC分类号： G06F12/06
CPC分类号： G11C16/344 , G11C16/04 , G11C16/345 , G11C29/52
摘要： A method for data storage includes performing an erasure operation on a group of analog memory cells (32). One or more of the memory cells in the group, which failed the erasure operation, are identified as erase-failed cells. A storage configuration that is used for programming the analog memory cells in the group is modified responsively to the identified erase-failed cells. Data is stored in the group of the analog memory cells using the modified storage configuration.
摘要翻译：一种用于数据存储的方法包括对一组模拟存储器单元（32）执行擦除操作。组中的一个或多个存储器单元（其在擦除操作中失败）被识别为擦除故障单元。用于对组中的模拟存储器单元进行编程的存储配置响应于所识别的擦除故障单元被修改。使用修改的存储配置将数据存储在模拟存储器单元的组中。

32. 发明申请

WO2006124122A2 ERASING NON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FOR SLOWER FRASING MEMORY CELLS 审中-公开
标题翻译：使用改变字线条件来擦除非易失性存储器以补偿较慢的存储器单元
公开(公告)号：WO2006124122A2
公开(公告)日：2006-11-23
申请号：PCT/US2006011651
申请日：2006-03-29
申请人： SANDISK CORP , HIGASHITANI MASAAKI
发明人： HIGASHITANI MASAAKI
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/3445 , G11C8/08 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： Voltage conditions applied to the memory cells of a non-volatile memory system are changed during erase operations in order to equalize the erase behavior of the select memory cells with other memory cells of the system that are being concurrently erased. The changed conditions can compensate for capacitively coupled voltages within a NAND string. After biasing a NAND string for an erase operation and beginning application of the erase voltage pulse, the word lines of one or more interior memory cells can be floated. By floating the selected interior word lines, the peak erase potential created across the tunnel dielectric region of the cells coupled thereto is decreased from its normal level. Consequently, the erase rates of these cells are slowed to substantially match that of the slower erasing end memory cells of the string. Different word lines can be floated at different times to alter the erase behavior of different memory cells b different amounts.
摘要翻译：施加到非易失性存储器系统的存储器单元的电压条件在擦除操作期间改变，以便均衡所选择的存储器单元与同时被擦除的系统的其它存储器单元的擦除行为。改变的条件可以补偿NAND串内的电容耦合电压。在为擦除操作偏置NAND串并开始施加擦除电压脉冲之后，一个或多个内部存储器单元的字线可被浮置。通过浮动选择的内部字线，在与其耦合的单元的隧道介电区域上产生的峰值擦除电位从其正常电平降低。结果，这些单元的擦除速率减慢，基本上与串中较慢的擦除端存储单元的擦除速率相匹配。不同的字线可以在不同的时间浮动以改变不同存储单元的擦除行为b不同的量。

33. 发明申请

WO2006105120A1 ERASING NON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OF MEMORY CELLS 审中-公开
标题翻译：使用个人验证和附加擦除存储器细胞的次序擦除非易失性记忆
公开(公告)号：WO2006105120A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011340
申请日：2006-03-29
申请人： SANDISK CORPORATION , HEMINK, Gerrit, Jan , KAMEI, Teruhiko
发明人： HEMINK, Gerrit, Jan , KAMEI, Teruhiko
IPC分类号： G11C16/34
CPC分类号： G11C16/344 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3468 , G11C16/3472 , G11C16/3477 , G11C2211/5621 , G11C2216/18
摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.
摘要翻译：一组非易失性存储元件被划分成用于擦除的子集，以避免擦除存储元件的擦除更快。整个元素组被擦除，直到该组元素的第一个子集被验证为被擦除为止。第一个子集可以包括更快的擦除单元。验证第一个子集包括从验证中排除第二个子集。在第一子集被验证为擦除之后，它们被禁止擦除，而第二子集被进一步擦除。当第二个子集被验证为擦除时，该组元素被验证为被擦除。验证该组元素被擦除可以包括排除第一子集验证或验证第一和第二子集在一起。使用不同的步长，这取决于要擦除和验证哪个子集，以便更有效和准确地擦除该组元素。

34. 发明专利

JP2014142988A Systems and methods for adaptive soft programming for non-volatile memory using temperature sensor 有权
标题翻译：使用温度传感器对非易失性存储器进行自适应软编程的系统和方法
公开(公告)号：JP2014142988A
公开(公告)日：2014-08-07
申请号：JP2013270487
申请日：2013-12-26
申请人： Freescale Semiconductor Inc , フリースケールセミコンダクターインコーポレイテッド
发明人： JON S CHOY
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/345 , G11C7/04 , G11C16/0483 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/5002
摘要： PROBLEM TO BE SOLVED: To reduce the amount of time required for soft programming procedure.SOLUTION: Erasing of a non-volatile memory (NVM) having an array of bit cells includes soft programming after an initial erasing of the bit cells. Over-erased bit cells are determined. A temperature is detected. A first soft program gate voltage based on the temperature is provided (502). Soft programming on the over-erased bit cells using the first soft program gate voltage is performed. Any remaining over-erased bit cells are identified (504). If there are any remaining over-erased bit cells, soft programming is performed (518) on the remaining over-erased bit cells using a second soft program gate voltage incremented from the first soft program gate voltage.
摘要翻译：要解决的问题：减少软编程过程所需的时间。解决方案：擦除具有位单元阵列的非易失性存储器（NVM）包括在位单元的初始擦除之后的软编程。确定过擦除的位单元。检测到温度。提供了基于温度的第一软程序栅极电压（502）。执行使用第一软程序栅极电压对过擦除位单元进行软编程。识别任何剩余的过擦除位单元（504）。如果存在任何剩余的过擦除位单元，则使用从第一软程序栅极电压增加的第二软程序栅极电压对剩余的超擦除位单元执行软编程（518）。

35. 发明专利

JP2007507830A To recover the over-erased cells, a memory device and a method therefor using the positive gate stress 有权
公开(公告)号：JP2007507830A
公开(公告)日：2007-03-29
申请号：JP2006533936
申请日：2004-09-16
申请人：アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated
发明人：マダーニアリカーン , ヘイ , シャーエドワード , タンパイロジクラチェト , ハミルトンダーリーン , リュウツィツェン , ダブリュ．ランドルフマーク , リーミミ
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要：複数のメモリセルから構成されたフラッシュ電気的消去可能読出し専用メモリ（ＥＥＰＲＯＭ）デバイス（１０）の消去方法は、複数のメモリセル（１０）をプリプログラミングするステップ（１００）と、複数のメモリセル（１０）に消去パルスを印加するステップ（１１０）と、を有し、これに消去検証（１２０）が続く。この消去検証（１２０）の後に、スレッショルド電圧が所定の最小レベル（Ｖ
ＴＭＩＮ）を下回るメモリセルのソフトプログラミング（１３５）と、複数のメモリセル（１０）への正のゲートストレスの印加（１３０）が続く。この消去方法は、過剰消去を防止し、スレッショルド電圧分布を低減する。

36. 发明申请

WO2014046887A1 BLOCK AND PAGE LEVEL BAD BIT LINE AND BITS SCREENING METHOD FOR NON-VOLATILE MEMORY 审中-公开
标题翻译： BLOCK AND PAGE LEVEL BAD BIT LINE AND BITS SCREENING METHOD FOR NON-VOLATILY MEMORY
公开(公告)号：WO2014046887A1
公开(公告)日：2014-03-27
申请号：PCT/US2013/058470
申请日：2013-09-06
申请人： SANDISK TECHNOLOGIES, INC. , WAN, Jun , LEI, Bo , PAN, Feng , SUN, Yongke
发明人： WAN, Jun , LEI, Bo , PAN, Feng , SUN, Yongke
IPC分类号： G11C29/02 , G11C29/44 , G11C7/10 , G11C11/56 , G11C16/10 , G11C16/24 , G11C16/34
CPC分类号： G11C16/349 , G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/10 , G11C16/24 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C29/025 , G11C29/44 , G11C2029/1204
摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
摘要翻译：编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。可以存储识别有缺陷的NAND串的状态位。要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的位翻转回其原始值。在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

37. 发明申请

WO2005038815A1 MEMORY DEVICE AND METHOD USING POSITIVE GATE STRESS TO RECOVER OVERERASED CELL 审中-公开
标题翻译：存储器件和使用正栅极应力来恢复过度电池的方法
公开(公告)号：WO2005038815A1
公开(公告)日：2005-04-28
申请号：PCT/US2004/030694
申请日：2004-09-16
申请人： ADVANCED MICRO DEVICES, INC. , HAMILTON, Darlene , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi , HSIA, Edward , TANPAIROJ, Kulachet , LEE, Mimi , MADHANI, Alykhan
发明人： HAMILTON, Darlene , LIU, Zhizheng , RANDOLPH, Mark, W. , HE, Yi , HSIA, Edward , TANPAIROJ, Kulachet , LEE, Mimi , MADHANI, Alykhan
IPC分类号： G11C16/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells (10) includes pre-programming (100) the plurality of memory cells (10), applying an erase pulse (110) to the plurality of memory cells (10) followed by an erase verification (120). The erase verification (120) is followed by soft programming (135) any memory cells having a threshold voltage below a predetermined minimum level (V TMIN ) and applying a positive gate stress (130) to the plurality of memory cells (10). The erase method prevents overerasing and provides a tightened threshold voltage distribution.
摘要翻译：擦除由多个存储单元（10）组成的闪存电可擦除只读存储器（EEPROM）器件的方法包括：对所述多个存储器单元（10）进行预编程（100），向所述多个存储器单元（10）施加擦除脉冲（110）多个存储器单元（10），随后进行擦除验证（120）。擦除验证（120）之后是具有低于预定最小电平（VTMIN）的阈值电压并向多个存储单元（10）施加正门应力（130）的任何存储器单元（135）进行软编程（135）。擦除方法可以防止过压，并提供紧固的阈值电压分布。

38. 发明申请

WO9524057A3 LOW VOLTAGE ONE TRANSISTOR FLASH EEPROM CELL USING FOWLER-NORDHEIM PROGRAMMING AND ERASE 审中-公开
标题翻译：使用FOWLER-NORDHEIM编程和擦除的低电压一个晶体管闪存EEPROM单元
公开(公告)号：WO9524057A3
公开(公告)日：1995-11-23
申请号：PCT/US9502240
申请日：1995-02-22
申请人： ROHM CORP
发明人： CHANG SHANG-DE , CHANG JIA-HWANG , CHOW EDWIN
IPC分类号： G11C16/04 , G11C16/02 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/34 , G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/345 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3459 , H01L27/115 , H01L29/7883
摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.
摘要翻译：在能够使用Fowler-Nordheim隧道进行编程和擦除并且能够使用低电压操作的单晶体管电可擦除可编程存储器件中，源极和漏极区域（14,12）中的每一个的部分与第一栅极介电层（18），并且所述互互电介质层（26）被选择为具有高介电常数，以便使浮置栅极（24），控制栅极（28），源极（14）和漏极（12）之间的电容耦合比最大化）。通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中的单元的逻辑状态。

39. 发明申请

WO1995024057A2 LOW VOLTAGE ONE TRANSISTOR FLASH EEPROM CELL USING FOWLER-NORDHEIM PROGRAMMING AND ERASE 审中-公开
标题翻译：使用FOWLER-NORDHEIM编程和擦除的低电压一个晶体管闪存EEPROM单元
公开(公告)号：WO1995024057A2
公开(公告)日：1995-09-08
申请号：PCT/US1995002240
申请日：1995-02-22
申请人： ROHM CORPORATION
发明人： ROHM CORPORATION , CHANG, Shang-De , CHANG, Jia-Hwang , CHOW, Edwin
IPC分类号： H01L29/788
CPC分类号： G11C16/345 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3459 , H01L27/115 , H01L29/7883
摘要： A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.
摘要翻译：能够使用Fowler-Nordheim隧道进行编程和擦除并能够使用低电压操作的单晶体管电可擦除可编程存储器件。源极和漏极区域中的每一个的部分与第一栅极介电层重叠，并且选择互互电介质层以具有高的介电常数，以便最大化浮动栅极，控制栅极，源极和漏极之间的电容耦合比。通过首先将单元格块升高到高电压阈值并单独降低所选单元格的电压阈值来设置阵列中的单元的逻辑状态。

40. 发明专利

JP2012198966A Nonvolatile semiconductor memory device and data erasing method for the same 审中-公开
标题翻译：非易失性半导体存储器件及其数据擦除方法
公开(公告)号：JP2012198966A
公开(公告)日：2012-10-18
申请号：JP2011063283
申请日：2011-03-22
申请人： Toshiba Corp , 株式会社東芝
发明人： TATEBE KEIJI , KASAI HISATOMO
IPC分类号： G11C16/02
CPC分类号： G11C16/16 , G11C16/3409 , G11C16/345
摘要： PROBLEM TO BE SOLVED: To reduce erasing time.SOLUTION: A nonvolatile semiconductor memory device 10 comprises: a memory cell array 11 having multiple pages which are provided in a common semiconductor region and respectively including multiple electrically-rewritable memory cells; a control circuit 23 for applying erasing operation to a selected page; and a verification circuit 18 for determining whether or not the memory cell array 11 has an excessively-erased memory cell after the erasing operation. The verification circuit 18 determines whether or not all memory cells of the selected page have a value equivalent to or greater than a threshold OEV1, and determines whether or not a memory cell in an erasing state, among non-selected pages, has a value equivalent to or greater than a threshold OEV2 lower than the threshold OEV1.
摘要翻译：要解决的问题：减少擦除时间。解决方案：非易失性半导体存储器件10包括：具有多个页面的存储单元阵列11，其设置在公共半导体区域中并且分别包括多个电可重写存储单元; 控制电路23，用于对所选择的页面进行擦除操作; 以及用于在擦除操作之后确定存储单元阵列11是否具有过度擦除的存储单元的验证电路18。验证电路18确定所选页面的所有存储单元是否具有等于或大于阈值OEV1的值，并且确定在未选择页中的擦除状态的存储单元是否具有等效值达到或大于低于阈值OEV1的阈值OEV2。版权所有（C）2013，JPO＆INPIT

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