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    • 31. 发明授权
    • Enclosed switchgear
    • 封闭式开关柜
    • US06927356B2
    • 2005-08-09
    • US10753080
    • 2004-01-08
    • Shinji SatoKenichi KoyamaMasahiro Arioka
    • Shinji SatoKenichi KoyamaMasahiro Arioka
    • H02B13/02H01H33/56H01H33/66H01H33/666
    • H01H33/666H01H33/565H01H33/6661H01H2033/6667
    • In a switchgear, oscillation of a moving current-carrying shaft and a moving contact of a vacuum valve is minimized, offset load on the contact surface is reduced, and friction the portion supporting the moving current-carrying shaft is reduced. A vacuum valve is disposed in a gas tank, one end of a moving current-carrying shaft integrally includes a moving contact of the vacuum valve, and a contact pressure adjusting spring is disposed on the other end of the moving current-carrying shaft. An operating rod extends through the gas tank, an operation mechanism is mounted on the operating rod outside the gas tank, an insulating rod is mounted inside the gas tank, and the contact pressure adjusting spring is joined to the insulating rod.
    • 在开关装置中,移动载流轴的振荡和真空阀的移动接触被最小化,接触表面上的偏移负载减小,并且支撑移动载流轴的部分的摩擦减小。 真空阀设置在气罐中,移动载流轴的一端一体地包括真空阀的移动触点,并且接触压力调节弹簧设置在移动载流轴的另一端。 操作杆延伸穿过气罐,操作机构安装在气罐外侧的操作杆上,绝缘杆安装在气罐内,接触压力调节弹簧与绝缘杆接合。
    • 37. 发明授权
    • Multi-level inverter with low loss snubbing circuits
    • 具有低损耗缓冲电路的多电平逆变器
    • US5841645A
    • 1998-11-24
    • US841388
    • 1997-04-30
    • Shinji Sato
    • Shinji Sato
    • H02M1/00H02M7/48H02M7/483H02M1/12
    • H02M7/487
    • A multi-level inverter, including an AC output terminal, at least four DC input terminals with different potentials having a first DC input terminal with a maximum potential and a second DC input terminal with a minimum potential, a positive arm connected between the first DC input terminal and the AC output terminal, and a negative arm connected between the second DC input terminal and the AC output terminal. Each of the positive and negative arms is composed of a plurality of series connected switching devices, respectively. The multi-level inverter further includes a plurality of clamp diodes, each connected between one of the DC input terminals other than the first and second DC input terminals and one of the positive and negative arms, respectively, a plurality of first snubber circuits, each composed of a series circuit of a snubber capacitor and a snubber diode and connected in parallel with one of the switching devices, respectively, and a plurality of discharging circuits, each composed of at least a resistor and connected between one of the first snubber circuits and the DC input terminals, respectively.
    • 一种包括AC输出端子的多电平逆变器,具有不同电位的至少四个DC输入端子,具有具有最大电位的第一DC输入端子和具有最小电位的第二DC输入端子,正极臂连接在第一DC 输入端子和交流输出端子,以及连接在第二直流输入端子和交流输出端子之间的负极。 正极和负极中的每一个分别由多个串联连接的开关装置组成。 多电平逆变器还包括多个钳位二极管,每个钳位二极管分别连接在除了第一和第二DC输入端子之外的一个DC输入端子和正极和负极臂中的一个之间,多个第一缓冲电路,每个 由缓冲电容器和缓冲二极管的串联电路分别与一个开关装置并联连接的多个放电电路,以及多个放电电路,每个放电电路由至少一个电阻器组成,并连接在第一缓冲电路之一和 直流输入端子。
    • 38. 发明授权
    • Time-adjustable delay circuit
    • 时间可调延时电路
    • US5768325A
    • 1998-06-16
    • US591129
    • 1996-01-25
    • Rieko YamamotoShinji Sato
    • Rieko YamamotoShinji Sato
    • G11C7/00G06F5/06H03K5/135H04J3/06H04L25/36
    • G06F5/06H03K5/135H04J3/062
    • A delay circuit externally adjustable for the delay time "n" as desired, which comprises a FIFO (FIRST-IN, FIRST-OUT) type memory, a self-load counter, and a decoder circuit. In addition to a data signal, an input clock is inputted to the memory as the write clock and the read clock. The self-load counter operates in synchronization with the input clock, and loads a setting of a load value-designating signal at a prescribed number of counts. The decoder circuit receives the output of the self-load counter which has a prescribed cycle, and outputs a reset signal with the same cycle to the memory. This cycle determines the delay time. The delay circuit allows a greatly reduced number of ICs used as compared with the prior art, even for increased delay times.
    • 延迟电路根据需要外部可调节延迟时间“n”,其包括FIFO(FIRST-IN,FIRST-OUT)型存储器,自负载计数器和解码器电路。 除了数据信号之外,输入时钟作为写时钟和读时钟输入到存储器。 自负载计数器与输入时钟同步工作,并以规定数量的计数加载负载值指定信号的设置。 解码器电路接收具有规定周期的自负载计数器的输出,并将相同周期的复位信号输出到存储器。 该周期决定延迟时间。 与现有技术相比,延迟电路允许大大减少使用的IC数量,即使增加延迟时间。