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31. 发明授权

US08283715B2 Method and apparatus for buried word line formation 有权
标题翻译：掩埋字线形成的方法和装置
公开(公告)号：US08283715B2
公开(公告)日：2012-10-09
申请号：US12855436
申请日：2010-08-12
申请人： Yung-Chang Lin , Sheng-Chang Liang
发明人： Yung-Chang Lin , Sheng-Chang Liang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L21/823487 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/0642 , H01L29/0653 , H01L29/66666 , H01L29/7827
摘要： An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.
摘要翻译：公开了一种具有存储单元的集成电路。具有存储单元的集成电路包括：设置在基板的字线沟槽中的字线; 布置在位线下方的字线下方且与字线正交延伸的位线; 以及分离层，其设置在所述位线沟槽中的位线之上，所述位线沟槽将所述字线与所述位线分离; 其中所述分离层的蚀刻速率接近所述衬底的蚀刻速率。

32. 发明授权

US07380026B2 Computer system with network signal level indication device 失效
标题翻译：带网络信号电平指示装置的计算机系统
公开(公告)号：US07380026B2
公开(公告)日：2008-05-27
申请号：US11257028
申请日：2005-10-25
申请人： Yung-Chang Lin
发明人： Yung-Chang Lin
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04L43/0817
摘要： A computer system with a device for indicating the network signal level of the LAN connected to the computer system is provided. The network signal level indication device includes a network signal level detection unit for detecting the signal level of the LAN connected to the computer and generating a set of network state signals, an indication unit interface circuit for receiving the set of network state signals generated by the network signal level detection unit, and a network signal level indication unit for receiving the set of network state signals and generating a light signal indicating the network signal level. The network signal level detection unit is the keyboard controller of the computer system.
摘要翻译：提供一种具有用于指示连接到计算机系统的LAN的网络信号电平的设备的计算机系统。网络信号电平指示装置包括网络信号电平检测单元，用于检测连接到计算机的LAN的信号电平并产生一组网络状态信号;指示单元接口电路，用于接收由该信号电平产生的一组网络状态信号网络信号电平检测单元和网络信号电平指示单元，用于接收一组网络状态信号并产生指示网络信号电平的光信号。网络信号电平检测单元是计算机系统的键盘控制器。

33. 发明授权

US06350646B1 Method for reducing thermal budget in node contact application 失效
标题翻译：节点接触应用中减少热预算的方法
公开(公告)号：US06350646B1
公开(公告)日：2002-02-26
申请号：US09484786
申请日：2000-01-18
申请人： Tung-Po Chen , Yung-Chang Lin
发明人： Tung-Po Chen , Yung-Chang Lin
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/76802 , H01L27/10855 , H01L27/10894
摘要： A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provided, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).
摘要翻译：公开了一种制造半导体器件的方法。该方法可以降低节点接触应用中的热预算。它主要包括以下过程。首先提供衬底，然后在衬底上形成电介质层。接下来，通过介电层到基板的顶表面的节点接触开口通过用光致抗蚀剂层涂覆介电层而形成，通过曝光和显影对具有节点接触图案的光致抗蚀剂层进行图案化，然后蚀刻介电层直到顶部使用所述图案化的光致抗蚀剂层作为掩模曝光所述衬底的表面。随后，去除光致抗蚀剂层。最后，通过快速热化学气相沉积（RTCVD）在节点接触开口的内壁上形成氮化硅层。

34. 发明授权

US6150205A Method of fabricating dual gate 有权
标题翻译：双门制造方法
公开(公告)号：US6150205A
公开(公告)日：2000-11-21
申请号：US227761
申请日：1999-01-08
申请人： Tung-Po Chen , Yung-Chang Lin
发明人： Tung-Po Chen , Yung-Chang Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a dual gate. A first conductive type region and a second conductive type region isolated by an isolation structure is provided. A polysilicon layer is formed on the first and the second conductive type regions. A diffusion layer containing second type conductive ions is formed on a second part of the polysilicon layer which covers the second conductive type region. First conductive ions are implanted into a part of the first conductive region which covers the first conductive type region. A first thermal process is performed. A metal layer is formed, and a second thermal process is performed, so that the metal layer is transformed into a metal silicide layer. A dielectric layer is formed on the metal layer. The dielectric layer, the metal silicide layer, diffusion layer, and the polysilicon layer are patterned to form a dual gate.
摘要翻译：一种制造双门的方法。提供了由隔离结构隔离的第一导电类型区域和第二导电类型区域。在第一和第二导电类型区域上形成多晶硅层。在覆盖第二导电类型区域的多晶硅层的第二部分上形成包含第二类型导电离子的扩散层。第一导电离子被注入到覆盖第一导电类型区域的第一导电区域的一部分中。执行第一热处理。形成金属层，进行第二热处理，使金属层转变为金属硅化物层。在金属层上形成电介质层。将电介质层，金属硅化物层，扩散层和多晶硅层图案化以形成双栅极。

35. 发明授权

US6124621A Structure of a spacer 有权
标题翻译：间隔物的结构
公开(公告)号：US6124621A
公开(公告)日：2000-09-26
申请号：US314528
申请日：1999-05-19
申请人： Yung-Chang Lin , Jih-Wen Chou , Tung-Po Chen
发明人： Yung-Chang Lin , Jih-Wen Chou , Tung-Po Chen
IPC分类号： H01L21/336 , H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L29/6656 , Y10S257/90 , Y10S257/915
摘要： A structure of a spacer in a semiconductor device is disclosed. Firstly, a gate without a spacer is provided on a substrate. A first insulating layer is formed on the sidewall of the gate. After a lightly doped drain is subsequently achieved in the substrate, a second insulating layer is formed on the first spacer. The process following this embodiment described above is to form a heavily doped drain in the substrate, then the whole MOSFET fabrication is completed. The present invention can enhance the stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.
摘要翻译：公开了半导体器件中的间隔物的结构。首先，在衬底上设置没有间隔物的栅极。第一绝缘层形成在栅极的侧壁上。在衬底中随后实现轻掺杂漏极之后，在第一间隔物上形成第二绝缘层。按照上述实施例描述的工艺是在衬底中形成重掺杂漏极，然后完成整个MOSFET制造。本发明可以提高门的电阻的稳定性并减少机器的污染。因此，MOSFET的制造的质量和效率将得到提高。

36. 发明授权

US08670300B2 Network device relating to digital subscriber line 有权
标题翻译：与数字用户线有关的网络设备
公开(公告)号：US08670300B2
公开(公告)日：2014-03-11
申请号：US13106885
申请日：2011-05-13
申请人： Yu-Sung Cho , Yung-Chang Lin
发明人： Yu-Sung Cho , Yung-Chang Lin
IPC分类号： G01R31/08 , H04B17/00
CPC分类号： H04L25/0264 , H04M11/062
摘要： A network device relating to a digital subscriber line (DSL) such as an asymmetrical DSL (ADSL) or a very high bit rate DSL (VDSL) is provided. In the present invention, the capacitors equipped into the network device are separated and grouped into two independent groups. When the network device runs out of power, the energy of one of the two independent groups is provided for generating the dying gasp signal, and the energy of the other of the two independent groups is provided for amplifying and transmitting the dying gasp signal to a Central Office (CO). Accordingly, the CO can be accurately known whether the network device runs out of power or not, and the respective capacitances of the two independent groups can be significantly reduced so as to reduce the cost of the network device.
摘要翻译：提供了与诸如不对称DSL（ADSL）或非常高比特率DSL（VDSL）的数字用户线（DSL）有关的网络设备。在本发明中，配置在网络装置中的电容器被分离并分组成两个独立的组。当网络设备耗尽电力时，提供两个独立组中的一个的能量用于产生垂死的气体信号，并且提供两个独立组中的另一个的能量用于放大并将垂直气体信号传输到中央办公室（CO）。因此，可以准确地知道CO网络设备是否断电，并且可以显着地减少两个独立组的各自的电容，从而降低网络设备的成本。

37. 发明申请

US20070275523A1 TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： TRENCH-CAPACITOR DRAM器件及其制造方法
公开(公告)号：US20070275523A1
公开(公告)日：2007-11-29
申请号：US11420222
申请日：2006-05-25
申请人： Yi-Nan Su , Yung-Chang Lin , Jun-Chi Huang
发明人： Yi-Nan Su , Yung-Chang Lin , Jun-Chi Huang
IPC分类号： H01L21/8244
CPC分类号： H01L27/1087
摘要： A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.
摘要翻译：公开了一种制造沟槽电容器的方法。提供具有第一焊盘层的衬底。 STI结构嵌入到第一焊盘层和衬底中。在第一焊盘层和STI结构上沉积第二焊盘层。两个相邻的沟槽被蚀刻到第一，第二焊盘层和半导体衬底中。蚀刻第二焊盘层和两个沟槽之间的STI结构的一部分以形成脊。衬套形成在沟槽的内表面上。在衬套上形成第一多晶硅层。在第一多晶硅层上形成电容器电介质层。两个相邻的沟槽被填充有第二多晶硅层。然后蚀刻第二多晶硅层直到暴露电容器介电层。制造工艺易于集成到SoC芯片。

38. 发明申请

US20070269946A1 Dynamic random access memory and fabrication method thereof 审中-公开
标题翻译：动态随机存取存储器及其制造方法
公开(公告)号：US20070269946A1
公开(公告)日：2007-11-22
申请号：US11437081
申请日：2006-05-19
申请人： Chien-Kuo Wang , Jun-Chi Huang , Ruey-Chyr Lee , Yung-Chang Lin
发明人： Chien-Kuo Wang , Jun-Chi Huang , Ruey-Chyr Lee , Yung-Chang Lin
IPC分类号： H01L21/8244
CPC分类号： H01L27/10861
摘要： A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above the first isolation structure and the bottom surface of the second isolation structure is lower than the top surface of the substrate. The periphery of the second isolation structure is beyond that of the first isolation structure. The transistors are disposed on the substrate respectively at two sides of the isolation structure. The trench capacitors are respectively disposed between the transistors and the isolation structures. A portion of the second isolation structure is disposed in the trench capacitor. The passing gates are completely disposed on the second isolation structure.
摘要翻译：提供了包括衬底，隔离结构，两个晶体管，两个沟槽电容器和两个通过栅极的动态随机存取存储器。包括第一隔离结构和第二隔离结构的隔离结构设置在基板中。第二隔离结构设置在第一隔离结构上方的基板中，并且第二隔离结构的底表面低于基板的顶表面。第二隔离结构的周边超出了第一隔离结构的周边。晶体管分别设置在隔离结构的两侧的基板上。沟槽电容器分别设置在晶体管和隔离结构之间。第二隔离结构的一部分设置在沟槽电容器中。通过的门完全设置在第二隔离结构上。

39. 发明申请

US20050156252A1 Method for forming a polycide gate and structure of the same 审中-公开
标题翻译：形成多晶硅栅极的方法及其结构
公开(公告)号：US20050156252A1
公开(公告)日：2005-07-21
申请号：US11011598
申请日：2004-12-15
申请人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
发明人： Yung-Chang Lin , Le-Tien Jung , Wen-Jeng Lin
IPC分类号： H01L21/28 , H01L21/3115 , H01L29/49 , H01L29/76 , H01L21/336
CPC分类号： H01L21/31155 , H01L21/28061 , H01L29/4916
摘要： The method of forming a polycide gate includes forming a pad oxide layer on a substrate. A first conductive layer is formed on the pad oxide layer. Subsequently, a first ion implantation into the first conductive layer is next performed to form deep implantation region of polysilicon. Successively, a second ion implantation into the first conductive layer is performed to form shallow implantation region of polysilicon, wherein the second ion type is the same as the first ion type. A second conductive layer formed on the first conductive layer. A further patterned photoresist layer is formed on the second conductive layer. Next, a dry etching process one time by way of using the patterned photoresist layer as an etching mask is performed to etch through in turn the second conductive layer, the first conductive layer and the pad oxide layer until forming a gate with double polysilicon implantation, thereby forming a polycide gate. Finally, the photoresist layer is then removed.
摘要翻译：形成多晶硅栅极的方法包括在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成第一导电层。随后，进行第一离子注入到第一导电层中以形成多晶硅的深注入区。接着，进行到第一导电层的第二离子注入以形成多晶硅的浅注入区，其中第二离子类型与第一离子类型相同。形成在第一导电层上的第二导电层。在第二导电层上形成另外的图案化光致抗蚀剂层。接下来，进行通过使用图案化光致抗蚀剂层作为蚀刻掩模一次的干蚀刻处理，以依次蚀刻第二导电层，第一导电层和衬垫氧化物层，直到形成具有双多晶硅注入的栅极，从而形成多晶硅栅极。最后，去除光致抗蚀剂层。

40. 发明申请

US20050106832A1 Dynamic random access memory cell and method for fabricating the same 有权
标题翻译：动态随机存取存储单元及其制造方法
公开(公告)号：US20050106832A1
公开(公告)日：2005-05-19
申请号：US10718896
申请日：2003-11-20
申请人： Yung-Chang Lin , Chia-Wen Liang , Chuan-Fu Wang
发明人： Yung-Chang Lin , Chia-Wen Liang , Chuan-Fu Wang
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10832 , H01L27/10867 , H01L29/66181
摘要： A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.
摘要翻译：提供DRAM单元及其制造方法。该方法包括：在衬底中形成沟槽; 在所述沟槽的表面上形成第一电容器电介质层; 在沟槽内形成导电层; 在所述衬底的表面上和所述导电层上形成第二电容器电介质层，其中所述第一和第二电容器电介质层周围的衬底用作底部电极; 在所述基板上形成突出电极，所述突出电极位于所述基板周围，并且覆盖所述沟槽和所述基板之间的接合部; 并且将所述突出电极和所述导电层电连接，所述导电层和所述突出电极为上电极。

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