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31. 发明授权

US07130223B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07130223B2
公开(公告)日：2006-10-31
申请号：US11251963
申请日：2005-10-18
申请人： Tetsuya Ishimaru , Nozomu Matsuzaki , Hitoshi Kume
发明人： Tetsuya Ishimaru , Nozomu Matsuzaki , Hitoshi Kume
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/792
摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.
摘要翻译：提高了非易失性半导体存储器件的特性。存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子，选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

32. 发明授权

US06711061B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06711061B2
公开(公告)日：2004-03-23
申请号：US10223488
申请日：2002-08-20
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

33. 发明申请

US20120286225A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120286225A1
公开(公告)日：2012-11-15
申请号：US13541097
申请日：2012-07-03
申请人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。

34. 发明授权

US08084810B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US08084810B2
公开(公告)日：2011-12-27
申请号：US12648796
申请日：2009-12-29
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L21/336
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

35. 发明授权

US07884348B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07884348B2
公开(公告)日：2011-02-08
申请号：US12754049
申请日：2010-04-05
申请人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L29/02 , H01L31/032
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞和堆叠在其上的插头。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

36. 发明申请

US20100193764A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100193764A1
公开(公告)日：2010-08-05
申请号：US12754049
申请日：2010-04-05
申请人： Masahiro MONIWA , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro MONIWA , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L45/00 , H01L27/105
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞和堆叠在其上的插头。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

37. 发明申请

US20070235710A1 Nonvolatile Memory 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20070235710A1
公开(公告)日：2007-10-11
申请号：US11630241
申请日：2005-07-04
申请人： Nozomu Matsuzaki , Motoyasu Terao
发明人： Nozomu Matsuzaki , Motoyasu Terao
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/128 , H01L45/1675
摘要： In non-volatile storage device using a variable resistance material, when a crystal state and a noncrystalline state co-exists in the variable resistance material, a crystallization time is shorted, resulting in decrease of the time to maintain information stored. Heat radiation is not rapidly performed during rewriting and thus it takes a long time to complete the rewriting due to a low thermal conductivity of a material contacting the variable resistance material. According to the present invention, a contact area between a variable resistance material and a lower electrode, and a contact area between the variable resistance material and an upper electrode are made equal to each other, thereby unifying a current path. The invention provides a structure in which a material having a high thermal conductivity is disposed so as to contact a sidewall of the variable resistance material, and its end portion is made to contact the lower electrode as well.
摘要翻译：在使用可变电阻材料的非挥发性存储装置中，当晶体状态和非结晶状态共存于可变电阻材料中时，结晶时间短路，导致维持信息存储的时间减少。在重写期间热辐射不能快速进行，因此由于接触可变电阻材料的材料的低导热性而需要很长时间来完成重写。根据本发明，使可变电阻材料与下部电极之间的接触面积与可变电阻材料与上部电极之间的接触面积相等，从而使电流路径均匀化。本发明提供了一种结构，其中具有高导热性的材料被设置成接触可变电阻材料的侧壁，并且其端部也与下电极接触。

38. 发明授权

US07180793B2 Semiconductor non-volatile storage device 有权
标题翻译：半导体非易失性存储设备
公开(公告)号：US07180793B2
公开(公告)日：2007-02-20
申请号：US11156538
申请日：2005-06-21
申请人： Nozomu Matsuzaki , Hideaki Kurata , Takayuki Kawahara
发明人： Nozomu Matsuzaki , Hideaki Kurata , Takayuki Kawahara
IPC分类号： G11C7/10
CPC分类号： G11C16/24 , G11C7/065 , G11C7/067 , G11C7/18 , G11C16/26 , G11C16/28 , G11C2207/002 , H01L27/0207 , H01L27/105 , H01L27/11526
摘要： A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used to drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.
摘要翻译：本发明的半导体非易失性存储装置，其使存储器单元直接驱动到本地位线，其中本地位线的输出由单独提供的信号放大晶体管的栅电极接收，并且信号放大晶体管用于驱动具有大负载能力的全局位线。由于具有高于存储单元的驱动功率的放大晶体管驱动全局位线的寄生电容，因此可以高速读出存储在存储单元中的信息。因此，存储装置用于存储用于控制微型计算机等的程序代码，从而提高系统性能。

39. 发明申请

US20060220100A1 Semicondudctor device 有权
标题翻译：半导体器件
公开(公告)号：US20060220100A1
公开(公告)日：2006-10-05
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

40. 发明申请

US20060051977A1 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device 有权
公开(公告)号：US20060051977A1
公开(公告)日：2006-03-09
申请号：US11266430
申请日：2005-11-04
申请人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
发明人： Tetsuo Adachi , Masataka Kato , Toshiaki Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , G11C11/5628 , G11C16/0466 , G11C16/10 , G11C16/3454 , H01L21/28061 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11546 , H01L29/6659 , H01L29/66825 , H01L29/7833
摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

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