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31. 发明授权

US06623912B1 Method to form the ring shape contact to cathode on wafer edge for electroplating in the bump process when using the negative type dry film photoresist 有权
标题翻译：在使用负型干膜光致抗蚀剂时，在凸块工艺中形成与晶片边缘上的阴极形成环形电镀方法
公开(公告)号：US06623912B1
公开(公告)日：2003-09-23
申请号：US09867094
申请日：2001-05-30
申请人： Kai-Ming Ching , Yu-Kung Hsiao , Sheng-Liang Pan , Kuo-Liang Lu
发明人： Kai-Ming Ching , Yu-Kung Hsiao , Sheng-Liang Pan , Kuo-Liang Lu
IPC分类号： G03F730
CPC分类号： H01L21/76885 , H01L24/11 , H01L2224/05568 , H01L2224/05573 , H01L2224/1147 , H01L2224/13099 , H01L2924/00014 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2224/05599
摘要： A method of clearing photoresist on a wafer edge, including the following steps. A wafer having a upper exposed conductive layer is provided. The wafer having a center, an edge and a ring-shaped area proximate the wafer edge. A photoresist layer is formed upon the exposed conductive layer. The photoresist layer is removed from within the ring-shaped area by a rinse process to expose the conductive layer within the ring-shaped area. An oxygen diffusion barrier layer is formed over the photoresist layer.
摘要翻译：一种在晶片边缘上清除光致抗蚀剂的方法，包括以下步骤。提供具有上暴露导电层的晶片。该晶片具有靠近晶片边缘的中心，边缘和环形区域。在暴露的导电层上形成光致抗蚀剂层。通过漂洗工艺从环形区域内去除光致抗蚀剂层，以暴露环形区域内的导电层。在光致抗蚀剂层上形成氧扩散阻挡层。

32. 发明授权

US06360756B1 Wafer rinse tank for metal etching and method for using 有权
标题翻译：用于金属蚀刻的晶圆冲洗槽和使用方法
公开(公告)号：US06360756B1
公开(公告)日：2002-03-26
申请号：US09325307
申请日：1999-06-03
申请人： Chie-Chi Chen , Tzu-Yang Chung , Szu-Yao Wang , Sheng-Liang Pan
发明人： Chie-Chi Chen , Tzu-Yang Chung , Szu-Yao Wang , Sheng-Liang Pan
IPC分类号： B08B704
CPC分类号： H01L21/67057 , B08B3/102 , Y10S134/902
摘要： A rinse tank for rinsing electronic substrates after a chemical process and a method for utilizing such rinse tank are provided. In the rinse tank, devices for performing a quick dump rinse; for performing a cascade overflow rinse and for feeding an inert gas bubbling are provided in the cavity of a single rinse tank. By utilizing the present invention novel rinse tank, the processing problems frequently observed in conventional rinse tanks where two rinse tanks are required for the quick dump rinse and for the cascade overflow rinse, such as particle re-deposition and a large floor space area requirement are eliminated. Furthermore, the wafer rinse process after a metal etching process can be accomplished in a total process time that is at least 2˜3 minutes shorter than that required by using conventional rinse tanks.
摘要翻译：提供了一种用于在化学过程之后冲洗电子基板的冲洗槽和用于使用这种冲洗槽的方法。在冲洗槽中，进行快速冲洗冲洗的装置; 在单个冲洗槽的空腔中设置用于进行级联溢流冲洗和用于进料惰性气体鼓泡的装置。通过利用本发明的新型漂洗槽，在常规冲洗槽中经常观察到的处理问题，其中需要两个漂洗槽用于快速冲洗冲洗和级联溢流冲洗，例如颗粒再沉积和大的占地空间面积要求，消除了此外，在金属蚀刻工艺之后的晶片冲洗过程可以在比使用常规冲洗槽所需的总处理时间短至少2〜3分钟的时间内完成。

33. 发明授权

US06878642B1 Method to improve passivation openings by reflow of photoresist to eliminate tape residue 失效
标题翻译：通过光刻胶回流来改善钝化开口以消除胶带残留的方法
公开(公告)号：US06878642B1
公开(公告)日：2005-04-12
申请号：US09679514
申请日：2000-10-06
申请人： Hung-Jen Hsu , Yu-Kung Hsiao , Chih-Kung Chang , Sheng-Liang Pan , Kuo-Liang Lu
发明人： Hung-Jen Hsu , Yu-Kung Hsiao , Chih-Kung Chang , Sheng-Liang Pan , Kuo-Liang Lu
IPC分类号： H01L21/311 , H01L21/31
CPC分类号： H01L21/31116 , H01L23/3171 , H01L2224/11472
摘要： A new method to form passivation openings in the manufacture of an integrated circuit device is achieved. The passivation openings have gradually sloping sidewalls that allow a protective tape to be completely removed without leaving adhesive residue. A semiconductor substrate is provided. A passivation layer is deposited. An organic photoresist layer is deposited overlying the passivation layer. The organic photoresist layer is patterned to expose the passivation layer in areas where passivation openings are planned. The organic photoresist layer is reflowed to create gradually sloping sidewalls on the organic photoresist layer. The passivation layer is etched through to from the passivation openings. The passivation openings are thereby formed with gradually sloping sidewalls. The organic photoresist layer is stripped away. A protective tape is applied overlying the passivation layer and the passivation openings. The protective tape is removed. The gradually sloping sidewalls on the passivation openings allow the protective tape to be completely removed without leaving adhesive residue in the manufacture of the integrated circuit device.
摘要翻译：实现了在制造集成电路器件中形成钝化开口的新方法。钝化开口具有逐渐倾斜的侧壁，其允许完全去除保护带而不留下粘合剂残留物。提供半导体衬底。沉积钝化层。沉积在钝化层上的有机光致抗蚀剂层。有机光致抗蚀剂层被图案化以在钝化开口被计划的区域中露出钝化层。有机光致抗蚀剂层被回流以在有机光致抗蚀剂层上产生逐渐倾斜的侧壁。从钝化开口蚀刻钝化层。因此钝化开口由逐渐倾斜的侧壁形成。剥离有机光致抗蚀剂层。施加保护带覆盖钝化层和钝化开口。取下保护胶带。钝化开口上逐渐倾斜的侧壁允许保护带被完全去除，而不会在集成电路器件的制造中留下残留粘合剂。

34. 发明授权

US06849533B2 Method for fabricating microelectronic product with attenuated bond pad corrosion 有权
标题翻译：用于制造具有减弱的焊盘腐蚀的微电子产品的方法
公开(公告)号：US06849533B2
公开(公告)日：2005-02-01
申请号：US10354697
申请日：2003-01-29
申请人： Chih-Kung Chang , Yu-Kung Hsiao , Sheng-Liang Pan , Fu-Tien Wong , Chin-Chen Kuo , Chung-Sheng Hsiung , Hung-Jen Hsu , Yi-Ming Dai , Po-Wen Lin , Te-Fu Tseng
发明人： Chih-Kung Chang , Yu-Kung Hsiao , Sheng-Liang Pan , Fu-Tien Wong , Chin-Chen Kuo , Chung-Sheng Hsiung , Hung-Jen Hsu , Yi-Ming Dai , Po-Wen Lin , Te-Fu Tseng
IPC分类号： H01L21/44 , H01L21/60
CPC分类号： H01L24/11 , H01L27/14621 , H01L27/14627 , H01L27/14685 , H01L2224/13099 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/12043 , H01L2924/14 , H01L2924/15787 , H01L2924/19042 , H01L2924/00
摘要： A method for fabricating a microelectronic product provides for forming a planarizing layer upon a bond pad and a topographic feature, both formed laterally separated over a substrate. The planarizing layer is formed with a diminished thickness upon the bond pad such that it may be readily etched to expose the bond pad while employing as a mask an additional layer formed over the topographic feature but not over the bond pad. The method is particularly useful for forming color filter sensor image array optoelectronic products with attenuated bond pad corrosion.
摘要翻译：用于制造微电子产品的方法提供了在接合焊盘和地形特征上形成平坦化层，两者均形成在衬底上横向分离。平坦化层在接合焊盘上形成为具有减小的厚度，使得其可以容易地蚀刻以暴露接合焊盘，同时使用形成在地形特征上但不在接合焊盘上的附加层作为掩模。该方法对于形成具有减弱的键合垫腐蚀的滤色器传感器图像阵列光电产品特别有用。

35. 发明授权

US06759276B1 Material to improve CMOS image sensor yield during wafer sawing 有权
标题翻译：在晶圆锯切期间提高CMOS图像传感器产量的材料
公开(公告)号：US06759276B1
公开(公告)日：2004-07-06
申请号：US10209149
申请日：2002-07-30
申请人： Hung-Jen Hsu , Yu-Kung Hsiao , Chih-Kung Chang , Sheng-Liang Pan
发明人： Hung-Jen Hsu , Yu-Kung Hsiao , Chih-Kung Chang , Sheng-Liang Pan
IPC分类号： H01L2144
CPC分类号： H01L27/14632 , H01L27/14627 , H01L27/14687
摘要： A new method is provided of treating the wafer prior to the process of singulating the wafer into individual die. A surface of the wafer over which CMOS image sensor devices have been created is coated with a layer of material that is non-soluble in water. The wafer is singulated by sawing through the layer of material that has been coated over the surface of the wafer and by then sawing through the wafer. The singulated die is then further processed by applying steps of die mount, wire bonding, surrounding the die in a mold compound and marking the package.
摘要翻译：提供了一种新的方法，在将晶片分离成单独的芯片的过程之前处理晶片。已经在其上形成CMOS图像传感器装置的晶片的表面涂覆有不溶于水的材料层。通过锯切已经涂覆在晶片表面上的材料层，然后通过晶片锯切将晶片分割。然后通过将模具安装，引线接合，将模具包围在模具化合物中并标记包装件的步骤进一步处理单模模具。

36. 发明授权

US06638688B2 Selective electroplating method employing annular edge ring cathode electrode contact 有权
公开(公告)号：US06638688B2
公开(公告)日：2003-10-28
申请号：US09726740
申请日：2000-11-30
申请人： Kai-Ming Ching , Sheng-Liang Pan , Hao-Wei Chang , Chun-Hong Chang , Yen-Ming Chen
发明人： Kai-Ming Ching , Sheng-Liang Pan , Hao-Wei Chang , Chun-Hong Chang , Yen-Ming Chen
IPC分类号： G03C556
CPC分类号： H01L21/2885 , C25D7/123 , C25D7/126 , G03F7/2026 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/13099 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/00 , H01L2224/05647 , H01L2224/05666 , H01L2224/05099
摘要： Within both a method for forming a patterned photoresist layer and a method for forming an electroplated patterned conductor layer while employing the patterned photoresist layer as a patterned photoresist plating mask layer there is first provided a substrate. There is then formed over the substrate a blanket photoresist layer formed of a negative photoresist material. There is then photoexposed the blanket photoresist layer to form a photoexposed blanket photoresist layer while employing a photoexposure apparatus which employs an annular edge ring exclusion apparatus positioned over an annular edge ring of the blanket photoresist layer and the substrate. Finally, there is then developed the photoexposed blanket photoresist layer to form a patterned photoresist layer having an annular edge ring excluded over the annular edge ring of the substrate. By employing within the context of the present invention the annular edge ring exclusion apparatus, the electroplated patterned conductor layer is formed with enhanced thickness uniformity.

37. 发明授权

US06417022B1 Method for making long focal length micro-lens for color filters 有权
标题翻译：制造彩色滤光片长焦微透镜的方法
公开(公告)号：US06417022B1
公开(公告)日：2002-07-09
申请号：US09547546
申请日：2000-04-12
申请人： Yu-Kung Hsiao , Sheng-Liang Pan , Bi-Cheng Chang , Kuo-Liang Lu
发明人： Yu-Kung Hsiao , Sheng-Liang Pan , Bi-Cheng Chang , Kuo-Liang Lu
IPC分类号： H01L2100
CPC分类号： H01L27/14685 , H01L27/14621 , H01L27/14627
摘要： A method for making long focal length micro-lens for color filters in CMOS image sensor applications and device made by the method are described. In the method, a layer of micro-lens material is first spin coated on top of a color filter, patterned by a photolithographic method into at least four discrete regions, and preferably at least nine discrete regions for each micro-lens with a pre-set spacing therein between. The discrete regions allow a smaller volume of micro-lens material to be used for forming the micro-lens in a subsequent reflow process. The micro-lens formed by the present invention novel method has a focal length of at least 7 &mgr;m, and preferably at least 10 &mgr;m such that a 0.35 &mgr;m technology CMOS image sensor utilizing two or three layers of metal conductors can be formed by the present invention method.
摘要翻译：描述了一种在CMOS图像传感器应用中制造用于滤色器的长焦距微透镜的方法和通过该方法制造的器件。在该方法中，首先将一层微透镜材料旋涂在滤色器的顶部，通过光刻方法图案化成至少四个离散的区域，并且优选地具有用于每个微透镜的至少九个离散区域，在其间设置间距。离散区域允许在随后的回流工艺中使用较小体积的微透镜材料来形成微透镜。通过本发明新颖的方法形成的微透镜的焦距至少为7μm，优选为至少10μm，使得利用两层或三层金属导体的0.35μm工艺CMOS图像传感器可以通过本发明形成发明方法。

38. 发明授权

US06395576B1 High efficiency color filter process to improve color balance in semiconductor array imaging devices 有权
标题翻译：高效率的彩色滤光片工艺可以改善半导体阵列成像装置的色彩平衡
公开(公告)号：US06395576B1
公开(公告)日：2002-05-28
申请号：US09593537
申请日：2000-06-14
申请人： Chih-Kung Chang , Yu-Kung Hsiao , Sheng-Liang Pan , Bii-Junq Chang
发明人： Chih-Kung Chang , Yu-Kung Hsiao , Sheng-Liang Pan , Bii-Junq Chang
IPC分类号： H01L2100
CPC分类号： H01L27/14609 , H01L27/14621 , H01L27/14623 , H01L27/14627
摘要： Formation of integrated color filters for gain-ratio balanced semiconductor array imagers using a spectrophotometric feedback control loop to adjust layer thickness during the deposition process is disclosed. The fabrication sequence of G/R/B conventionally used in Prior Art has been changed to B/R/G or B/G/R to enable the process to adapt to yielding specified color gain-ratio values without the need for integrated circuit redesign. A high efficiency color filter process is demonstrated wherein the additional neutral-density attenuator layers and/or spacer layers required in Prior Art fabrication methods are eliminated. The disclosed process is shown to enable high-precision thickness control of the color filter layers. Blue coating lift-off problems and the steric effect associated with successive depositions of color layers having step-height variations are eliminated. Statistical process control (SPC) is optimized by calibration of the color balance gain-ratio using the product photodiode arrays and amplifier integrated circuits with a real-time spectrophotometric feedback control-loop during the dye or pigment layer deposition process.
摘要翻译：公开了用于增益比平衡的半导体阵列成像器的集成滤色器的形成，其使用分光光度反馈控制环来在沉积过程中调节层厚度。现有技术中常规使用的G / R / B的制造顺序已经改变为B / R / G或B / G / R，以使该工艺适应于产生指定的颜色增益比值，而不需要集成电路重新设计。证明了高效率滤色器工艺，其中消除了现有技术制造方法中所需的附加中性密度衰减器层和/或间隔层。所公开的过程被示出为使得能够对滤色器层进行高精度的厚度控制。消除蓝色涂层剥离问题和与具有阶跃高度变化的彩色层的连续沉积相关的空间效应。通过使用产品光电二极管阵列和放大器集成电路通过在染料或颜料层沉积过程中具有实时分光光度反馈控制环来校准色平衡增益比来优化统计过程控制（SPC）。

39. 发明授权

US6143579A Efficient method for monitoring gate oxide damage related to plasma etch chamber processing history 有权
标题翻译：用于监测与等离子体蚀刻室处理历史有关的栅极氧化物损伤的高效方法
公开(公告)号：US6143579A
公开(公告)日：2000-11-07
申请号：US298936
申请日：1999-04-26
申请人： Chia-Der Chang , Chi-Hung Liao , Dean-E Lin , Sheng-Liang Pan
发明人： Chia-Der Chang , Chi-Hung Liao , Dean-E Lin , Sheng-Liang Pan
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , H01L22/12 , H01L2924/0002
摘要： It has been observed that, when a commercial plasma etcher is used for multiple etching tasks involving a variety of products, the amount of plasma damage incurred depends upon the chamber history of the etching tool. Thus, etching a gate sidewall spacer on a damage sensitive product, for example, in a MOSFET product with very thin gate oxide, may result in significant degradation of the gate oxide if the plasma etching tool had been used to etch vias on another type product in the preceding job. A method for monitoring and recording the chamber history and ascertaining the status of a plasma etching tool with regard to the tendency of said tool to introduce plasma damage in thin gate and tunnel oxide layers is disclosed. The method includes an a oxide damage monitor wafer which contains arrays of simple test devices. The monitor wafers can be partially formed and banked for later use. The test devices comprise a polysilicon plate partially covering a gate oxide. A conformal oxide is formed over the structure and the wafer is subjected to a spacer etch in the plasma etching tool being appraised. Dielectric breakdown the thin oxide is measured and the data is compared to a chamber history of the etcher. Those etching procedures which adversely affect the chamber are identified. Once a chamber history is established, the etcher can be expeditiously scheduled and the incidence of jobs lost to oxide damage greatly reduced.
摘要翻译：已经观察到，当商业等离子体蚀刻机用于涉及各种产品的多次蚀刻任务时，所产生的等离子体损伤的量取决于蚀刻工具的腔室历史。因此，如果已经使用等离子体蚀刻工具蚀刻另一种类型产品上的通孔，则蚀刻损伤敏感产品上的栅极侧壁间隔物（例如，具有非常薄的栅极氧化物的MOSFET产品）可能导致栅极氧化物的显着降解在前面的工作。公开了一种用于监测和记录室历史并确定等离子体蚀刻工具关于所述工具在薄栅和隧道氧化物层中引入等离子体损伤的趋势的方法。该方法包括含有简单测试装置阵列的氧化物损伤监测晶片。显示器晶片可以部分地形成并分组以供以后使用。测试装置包括部分覆盖栅极氧化物的多晶硅板。在结构上形成共形氧化物，并且在评估的等离子体蚀刻工具中对晶片进行间隔蚀刻。测量介电击穿薄氧化物，并将数据与蚀刻器的室历史进行比较。识别对腔室有不利影响的蚀刻过程。一旦建立了房间历史，就可以迅速安排蚀刻器，大大减少对氧化物损失造成的作业的发生。

40. 发明授权

US6107202A Passivation photoresist stripping method to eliminate photoresist extrusion after alloy 有权
标题翻译：钝化光刻胶剥离方法消除合金后的光致抗蚀剂挤出
公开(公告)号：US6107202A
公开(公告)日：2000-08-22
申请号：US152349
申请日：1998-09-14
申请人： Chih-Kang Chiu , Sheng-Liang Pan
发明人： Chih-Kang Chiu , Sheng-Liang Pan
IPC分类号： H01L21/311 , H01L21/768 , H01L21/308
CPC分类号： H01L21/31133 , H01L21/7682 , Y10S438/906 , Y10S438/948 , Y10S438/963
摘要： A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.
摘要翻译：在光致抗蚀剂带之前使用NMP溶剂条的加热处理之前，从钝化层18中的键孔17剥离正性光致抗蚀剂的方法。该方法由以下5个步骤总结如下：（1）光致抗蚀剂条1（例如EKC 830），（2）光致抗蚀剂条2（例如EKC 830光致抗蚀剂剥离剂），（3）N-甲基-2-吡咯烷酮（ NMP）溶剂条状搅拌（溶剂优选在光致抗蚀剂剥离剂（1和2）中相同的溶剂（4）NMP溶剂条搅拌和（5）H 2 O漂洗NMP溶剂条（3）和（4）残留物（16，图1）。这防止了在金属线14退火的同时形成光刻胶挤出物24。

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