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    • 32. 发明授权
    • Pulse generation circuit and modulator
    • 脉冲发生电路和调制器
    • US07898354B2
    • 2011-03-01
    • US12305546
    • 2007-06-20
    • Shigeru KobayashiMichiaki MatsuoSuguru Fujita
    • Shigeru KobayashiMichiaki MatsuoSuguru Fujita
    • H03K7/02
    • H03C1/36H03K7/08
    • It is an object of the invention to provide a pulse generation circuit and a modulator for realizing a high On/Off ratio in a small circuit scale and with lower power consumption. A short pulse generation circuit according to the invention includes an oscillator 101, a control signal generation circuit 102, an intermittent frequency multiplier 103, a filter 104, and an output terminal 105. The oscillator 101 and the intermittent frequency multiplier 103 are active circuits implemented as active elements. A continuous signal is output from the oscillator 101 and is input to the intermittent frequency multiplier 103 and the intermittent frequency multiplier 103 intermittently operates according to a control signal output from the control signal generation circuit 102, thereby generating a short pulse signal, and a spurious component is removed through the filter.
    • 本发明的目的是提供一种用于在小电路规模和低功耗下实现高开/关比的脉冲发生电路和调制器。 根据本发明的短脉冲发生电路包括振荡器101,控制信号产生电路102,间歇倍频器103,滤波器104和输出端子105.振荡器101和间歇倍频器103是实现的有源电路 作为活动元素。 从振荡器101输出连续信号,并输入到间歇倍频器103,并且间歇频率乘法器103根据从控制信号发生电路102输出的控制信号间歇地工作,从而产生短脉冲信号和假 组件通过过滤器被去除。
    • 33. 发明申请
    • Pulse-Sync Demodulator
    • 脉冲同步解调器
    • US20100246660A1
    • 2010-09-30
    • US12374737
    • 2007-07-27
    • Michiaki MatsuoHideki AoyagiHitoshi AsanoKazuya Toki
    • Michiaki MatsuoHideki AoyagiHitoshi AsanoKazuya Toki
    • H03K9/04
    • H04L7/033H03L7/0807H03L7/0812H04B1/717H04B1/7183H04L7/0037
    • A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.
    • 基于开关键控调制方式的接收脉冲信号由频率为传输速率的二分之一的时钟信号操作的AD转换部分交替采样。 在同步中,采样定时调整部分中的延迟量彼此不同,从而对符号脉冲中两个不同点的相位进行采样。 根据采样值的比较结果调整可变延迟部分的延迟量,从而实现同步。 在解调时,保持可变延迟部分中的延迟量,并将采样定时调整部分中的延迟量切换到相同的值,并且对符号脉冲进行交替采样。 对采样值进行阈值判定,对判定结果进行并行到串行转换,从而得到解调输出。
    • 34. 发明申请
    • PULSE TRANSMITTING DEVICE, PULSE RECEIVING DEVICE, PULSE COMMUNICATION SYSTEM, AND PULSE COMMUNICATION METHOD
    • 脉冲发射装置,脉冲接收装置,脉冲通信系统和脉冲通信方法
    • US20100020864A1
    • 2010-01-28
    • US12374994
    • 2007-07-12
    • Michiaki MatsuoHitoshi AsanoHideki AoyagiKazuaki TakahashiYew Soo Eng
    • Michiaki MatsuoHitoshi AsanoHideki AoyagiKazuaki TakahashiYew Soo Eng
    • H03K7/04H04L27/06
    • H04L25/4906H04B1/7172H04B1/719H04L25/4902
    • A pulse transmitting device is provided to avoid interference between pulses due to multipath influence even in a high speed pulse transmission that is typical of a UWB by making use of a relatively simple method and to improve receiving quality. In the device, a pulse adjusting unit (110) generates pulses in response to transmitting data, a non-use interval setting unit (120) sets up a non-use interval where the pulses generated by the pulse adjusting unit (110) are not transmitted on the basis of a delay time that a delayed pulse caused by the multipath delays from a main pulse and takes until arriving at a communication partner. A pulse position adjusting unit (130) adjusts a pulse position not to transmit the pulses during the non-use pulse interval. An RF transmitting unit (140) converts the pulse, the position of which is adjusted by the pulse position adjusting unit, to a wireless frequency band and transmits a pulse wireless signal after the conversion to the communication partner.
    • 提供脉冲发送装置,即使在UWB的典型的高速脉冲传输中,通过利用相对简单的方法并且提高接收质量,也可以避免由于多路径影响引起的脉冲之间的干扰。 在该装置中,脉冲调整单元(110)响应于发送数据产生脉冲,不使用间隔设定单元(120)设定由脉冲调整单元(110)生成的脉冲不是的非使用间隔 基于由主脉冲的多径延迟引起的延迟脉冲的延迟时间发送,并且直到到达通信伙伴。 脉冲位置调整单元(130)调整在不使用脉冲间隔期间不发送脉冲的脉冲位置。 RF发送单元(140)将其位置由脉冲位置调整单元调整的脉冲转换为无线频带,并且在转换到通信对方之后发送脉冲无线信号。
    • 38. 发明申请
    • MULTIPLYING OSCILLATOR AND WIRELESS APPARATUS IN WHICH THE SAME IS INSTALLED
    • 多功能振荡器及其安装的无线设备
    • US20100090770A1
    • 2010-04-15
    • US12519654
    • 2007-12-19
    • Michiaki Matsuo
    • Michiaki Matsuo
    • H03L7/24H03B7/06
    • H01P7/08H03B1/04H03B5/1215H03B5/1228H03B2200/007H03B2202/012
    • An object of the invention is to provide a multiplying oscillator capable of generating a high frequency signal by small circuit scale and power consumption in an oscillator for generating a signal with a frequency of a microwave band or more, and a local oscillator using this multiplying oscillator. A multiplying oscillator of the invention obtains a frequency signal four times or more a fundamental wave by adding a frequency adjusting unit 40 having a function of suppressing second harmonic of the fundamental wave to a resonance unit 20 in a multiplying oscillator which constructs an oscillator for connecting two negative resistance units 10 to 11 to the resonance unit 20 and generating a signal A and a signal B of mutually opposite phases in the fundamental wave and synthesizes the signal A and the signal B in phase in a synthetic unit 30 and obtains an oscillation signal output.
    • 本发明的目的是提供一种乘法振荡器,其能够通过小型电路规模产生高频信号,并且在用于产生具有微波频带或更多频率的信号的振荡器中产生功率消耗,以及使用该乘法振荡器的本地振荡器 。 本发明的乘法振荡器通过在构成连接用振荡器的乘法振荡器中,将具有抑制基波的二次谐波的功能的频率调整单元40附加到谐振单元20,从而获得基波的四倍以上的频率信号 两个负电阻单元10至11耦合到谐振单元20,并产生信号A和基波相互相反的信号B,并在合成单元30中相位合成信号A和信号B,并获得振荡信号 输出。
    • 39. 发明授权
    • Variable matching circuit
    • 可变匹配电路
    • US07633355B2
    • 2009-12-15
    • US11568188
    • 2005-04-19
    • Michiaki Matsuo
    • Michiaki Matsuo
    • H03H7/38
    • H03H7/40H04B1/18
    • A variable matching circuit includes a variable capacitance circuit formed of a capacitor coupled to varactor diode and provided between terminals, and a resonator-type circuit includes a plurality of inductors and a variable capacitance circuit formed of a capacitor and a varactor diode. The inductors and the variable capacitance circuit are coupled in parallel together. The resonator-type circuit is connected in shunt with the terminal. The foregoing structure forms an L-type matching circuit. The bias of the varactor diodes can be thus varied, and plural values of the inductance of the resonator-type circuit can be switched over with a FET. The variable matching circuit can electrically control an impedance conversion available for wider ranges of frequency bandwidths.
    • 可变匹配电路包括由耦合到变容二极管并且设置在端子之间的电容器形成的可变电容电路,并且谐振器型电路包括多个电感器和由电容器和变容二极管形成的可变电容电路。 电感器和可变电容电路并联在一起。 谐振器型电路与端子分流连接。 上述结构形成L型匹配电路。 因此可以改变变容二极管的偏置,并且谐振器型电路的电感的多个值可以用FET切换。 可变匹配电路可以电控制可用于更宽范围的频率带宽的阻抗转换。