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1. 发明授权

US08406346B2 Code error detecting device, wireless system and code error detecting method 有权
标题翻译：代码错误检测装置，无线系统和代码错误检测方法
公开(公告)号：US08406346B2
公开(公告)日：2013-03-26
申请号：US12305570
申请日：2007-06-20
申请人： Kazuaki Takahashi , Suguru Fujita , Michiaki Matsuo , Yutaka Murakami , Satoshi Hasako
发明人： Kazuaki Takahashi , Suguru Fujita , Michiaki Matsuo , Yutaka Murakami , Satoshi Hasako
IPC分类号： H03D3/22 , H04L7/00 , H04B7/208
CPC分类号： H04L27/06 , H04L1/0045 , H04L1/06 , H04L1/1812 , H04L1/1829 , H04L25/03171 , H04L25/067
摘要： A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna (121) for receiving a on-off keying modulated pulse and its code-reversed pulse, a pulse detector (124) for outputting detected data in accordance with the pulses, a code comparing unit (128) for comparing each code of first received data (R1) with one of second received data (R2), wherein the first and second received data are derived from the output detected data, and an error detecting unit (129) for detecting an error of each code from a comparison result (D2) indicative of a result compared in the code comparing unit (128).
摘要翻译：公开了一种可以更精确地检测由于延迟波引起的码错误的码错误检测装置。代码错误检测装置包括用于接收开关键控调制脉冲及其代码反转脉冲的接收天线（121），用于根据脉冲输出检测数据的脉冲检测器（124），代码比较单元（128 ），用于将第一接收数据（R1）的每个代码与第二接收数据（R2）中的一个进行比较，其中从所述输出检测数据导出第一和第二接收数据;以及错误检测单元（129），用于检测来自代码比较单元（128）中比较结果的比较结果（D2）的每个代码。

2. 发明申请

US20090177954A1 CODE ERROR DETECTING DEVICE, WIRELESS SYSTEM AND CODE ERROR DETECTING METHOD 有权
标题翻译：代码错误检测设备，无线系统和代码错误检测方法
公开(公告)号：US20090177954A1
公开(公告)日：2009-07-09
申请号：US12305570
申请日：2007-06-20
申请人： Kazuaki Takahashi , Suguru Fujita , Michiaki Matsuo , Yutaka Murakami , Satoshi Hasako
发明人： Kazuaki Takahashi , Suguru Fujita , Michiaki Matsuo , Yutaka Murakami , Satoshi Hasako
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L27/06 , H04L1/0045 , H04L1/06 , H04L1/1812 , H04L1/1829 , H04L25/03171 , H04L25/067
摘要： A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna (121) for receiving a on-off keying modulated pulse and its code-reversed pulse, a pulse detector (124) for outputting detected data in accordance with the pulses, a code comparing unit (128) for comparing each code of first received data (R1) with one of second received data (R2), wherein the first and second received data are derived from the output detected data, and an error detecting unit (129) for detecting an error of each code from a comparison result (D2) indicative of a result compared in the code comparing unit (128).
摘要翻译：公开了一种可以更精确地检测由于延迟波引起的码错误的码错误检测装置。代码错误检测装置包括用于接收开关键控调制脉冲及其代码反转脉冲的接收天线（121），用于根据脉冲输出检测数据的脉冲检测器（124），代码比较单元（128 ），用于将第一接收数据（R1）的每个代码与第二接收数据（R2）中的一个进行比较，其中从所述输出检测数据导出第一和第二接收数据;以及错误检测单元（129），用于检测来自代码比较单元（128）中比较结果的比较结果（D2）的每个代码。

3. 发明申请

US20100266053A1 WIRELESS COMMUNICATION METHOD, RADIO TRANSMITTER APPARATUS AND RADIO RECEIVER APPARATUS 审中-公开
标题翻译：无线通信方法，无线发射机设备和无线接收设备
公开(公告)号：US20100266053A1
公开(公告)日：2010-10-21
申请号：US12742061
申请日：2008-11-27
申请人： Takenori Sakamoto , Taisuke Matsumoto , Satoshi Hasako , Suguru Fujita , Masashi Kobayashi , Zhan Yu
发明人： Takenori Sakamoto , Taisuke Matsumoto , Satoshi Hasako , Suguru Fujita , Masashi Kobayashi , Zhan Yu
IPC分类号： H04L27/00 , H04L27/20 , H04L27/06
CPC分类号： H04L25/0224 , H04L27/0008 , H04L27/18 , H04L27/2071
摘要： A wireless communication method, a radio transmitter apparatus and a radio receiver apparatus wherein a signal sequence, which is used in a reception process using a first modulation scheme and can be generated from a signal sequence prepared for a reception process and used in a second modulation scheme, is employed, thereby achieving a performance to a similar extent to the reception process performance using the second modulation scheme. A radio transmitter apparatus (20) uses a first modulation scheme (e.g., OOK modulation scheme) to sequentially transmit, as a first sequence, both a sub-sequence a1(n), which is identical with a second sequence a(n) designed for use in a second modulation scheme (e.g., BPSK modulation scheme), and a sub-sequence a2(n), the bits of which are reverse to those of the second sequence a(n), in a time division manner. A radio receiver apparatus (30) detects the sub-sequence a1(n) and sub-sequence a2(n) in a received signal to send the detection result to the following stage for a signal processing.
摘要翻译：一种无线通信方法，无线发送装置以及无线接收装置，其特征在于，在使用第一调制方式的接收处理中使用的信号序列，可以从为接收处理而准备的信号序列生成并在第二调制中使用的信号序列方案，从而实现与使用第二调制方案的接收处理性能相似程度的性能。无线电发射机装置（20）使用第一调制方案（例如，OOK调制方案）作为第一序列顺序地发送与被设计的第二序列a（n）相同的子序列a1（n）用于第二调制方案（例如，BPSK调制方案）以及子序列a2（n），它们的比特以时分方式与第二序列a（n）的比特相反。无线接收装置（30）检测接收信号中的子序列a1（n）和子序列a2（n），将检测结果发送到后续的信号处理阶段。

4. 发明授权

US07898354B2 Pulse generation circuit and modulator 有权
标题翻译：脉冲发生电路和调制器
公开(公告)号：US07898354B2
公开(公告)日：2011-03-01
申请号：US12305546
申请日：2007-06-20
申请人： Shigeru Kobayashi , Michiaki Matsuo , Suguru Fujita
发明人： Shigeru Kobayashi , Michiaki Matsuo , Suguru Fujita
IPC分类号： H03K7/02
CPC分类号： H03C1/36 , H03K7/08
摘要： It is an object of the invention to provide a pulse generation circuit and a modulator for realizing a high On/Off ratio in a small circuit scale and with lower power consumption. A short pulse generation circuit according to the invention includes an oscillator 101, a control signal generation circuit 102, an intermittent frequency multiplier 103, a filter 104, and an output terminal 105. The oscillator 101 and the intermittent frequency multiplier 103 are active circuits implemented as active elements. A continuous signal is output from the oscillator 101 and is input to the intermittent frequency multiplier 103 and the intermittent frequency multiplier 103 intermittently operates according to a control signal output from the control signal generation circuit 102, thereby generating a short pulse signal, and a spurious component is removed through the filter.
摘要翻译：本发明的目的是提供一种用于在小电路规模和低功耗下实现高开/关比的脉冲发生电路和调制器。根据本发明的短脉冲发生电路包括振荡器101，控制信号产生电路102，间歇倍频器103，滤波器104和输出端子105.振荡器101和间歇倍频器103是实现的有源电路作为活动元素。从振荡器101输出连续信号，并输入到间歇倍频器103，并且间歇频率乘法器103根据从控制信号发生电路102输出的控制信号间歇地工作，从而产生短脉冲信号和假组件通过过滤器被去除。

5. 发明申请

US20090174494A1 PULSE GENERATION CIRCUIT AND MODULATOR 有权
标题翻译：脉冲发生电路和调制器
公开(公告)号：US20090174494A1
公开(公告)日：2009-07-09
申请号：US12305546
申请日：2007-06-20
申请人： Shigeru Kobayashi , Michiaki Matsuo , Suguru Fujita
发明人： Shigeru Kobayashi , Michiaki Matsuo , Suguru Fujita
IPC分类号： H03B19/00 , H03K7/08
CPC分类号： H03C1/36 , H03K7/08
摘要： It is an object of the invention to provide a pulse generation circuit and a modulator for realizing a high On/Off ratio in a small circuit scale and with lower power consumption. A short pulse generation circuit according to the invention includes an oscillator 101, a control signal generation circuit 102, an intermittent frequency multiplier 103, a filter 104, and an output terminal 105. The oscillator 101 and the intermittent frequency multiplier 103 are active circuits implemented as active elements. A continuous signal is output from the oscillator 101 and is input to the intermittent frequency multiplier 103 and the intermittent frequency multiplier 103 intermittently operates according to a control signal output from the control signal generation circuit 102, thereby generating a short pulse signal, and a spurious component is removed through the filter.
摘要翻译：本发明的目的是提供一种用于在小电路规模和低功耗下实现高开/关比的脉冲发生电路和调制器。根据本发明的短脉冲发生电路包括振荡器101，控制信号产生电路102，间歇倍频器103，滤波器104和输出端子105.振荡器101和间歇倍频器103是实现的有源电路作为活动元素。从振荡器101输出连续信号，并输入到间歇倍频器103，并且间歇频率乘法器103根据从控制信号发生电路102输出的控制信号间歇地工作，从而产生短脉冲信号和假组件通过过滤器被去除。

6. 发明授权

US07898312B2 Variable delay apparatus 失效
标题翻译：可变延迟装置
公开(公告)号：US07898312B2
公开(公告)日：2011-03-01
申请号：US12376024
申请日：2007-08-07
申请人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
发明人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.
摘要翻译：本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。

7. 发明申请

US20090315605A1 VARIABLE DELAY APPARATUS 失效
标题翻译：可变延迟装置
公开(公告)号：US20090315605A1
公开(公告)日：2009-12-24
申请号：US12376024
申请日：2007-08-07
申请人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
发明人： Hideki Aoyagi , Hitoshi Asano , Kazuya Toki , Michiaki Matsuo , Suguru Fujita
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.
摘要翻译：本发明的目的是提供一种可变延迟装置，其中即使在可变延迟装置的延迟量之后立即改变与设置的延迟量不同的定时信号也不被输出。本发明的可变延迟装置包括：具有N（N是自然数）延迟元件101a至101n的可变延迟块108和N个选择器102a至102n; 具有N个延迟元件103a〜103n的可变延迟块109和N个选择器104a〜104n; 在选择信号105a至105n和106a至106n改变之后，并且在达到由可变延迟块108,109设置的延迟量的输出定时之后，通过选择器107切换要输出的信号，从而避免了在延迟量变化之后立即输出与设定的延迟量不同的定时的信号作为输出信号的情况。

8. 发明授权

US07940841B2 Modulating circuit, transmitting apparatus using the same, receiving apparatus and communication system 有权
标题翻译：调制电路，使用该调制电路的发送装置，接收装置和通信系统
公开(公告)号：US07940841B2
公开(公告)日：2011-05-10
申请号：US11718570
申请日：2005-11-04
申请人： Masahiro Mimura , Kazuaki Takahashi , Suguru Fujita , Yoshinori Kunieda , Noriyuki Ueki
发明人： Masahiro Mimura , Kazuaki Takahashi , Suguru Fujita , Yoshinori Kunieda , Noriyuki Ueki
IPC分类号： H03K7/04
CPC分类号： H04B1/7174 , H03K7/04 , H04B1/71635 , H04B1/71637 , H04B1/7176 , H04L25/4902 , H04L27/0004
摘要： A communication system includes a modulating circuit to increase the amount of information to be transmitted, a transmitting apparatus capable of easily generating a desired waveform even for any very short wavelets, a receiving apparatus capable of easily separating wavelets even if the intervals thereof are narrow. The modulating circuit includes clock generating, transmission signal generating, control signal generating, delay and wavelet generating parts. The clock generating part generates a clock signal at predetermined time interval “Tp”. The transmission signal generating part generates a transmission signal at interval “Tp”. The control signal generating part outputs a control signal of a predetermined duration based on the clock signal. The delay part generates the control signal as a delay signal that has been delayed by a delay amount based on the transmission signal. The wavelet generating part generates a wavelet at the generation timing of the delay signal.
摘要翻译：一种通信系统包括：调制电路，用于增加要发送的信息量;即使对于任何非常短的小波也能够容易地产生期望的波形的发送装置，即使其间隔窄也能够容易地分离小波的接收装置。调制电路包括时钟产生，发送信号产生，控制信号产生，延迟和小波发生部分。时钟产生部分以预定时间间隔“Tp”产生时钟信号。发送信号生成部以间隔“Tp”生成发送信号。控制信号产生部分基于时钟信号输出预定持续时间的控制信号。延迟部分产生作为延迟信号的控制信号，该延迟信号已经基于发送信号被延迟延迟量。小波生成部在延迟信号的产生定时产生小波。

9. 发明申请

US20100166037A1 UWB TRANSMISSION APPARATUS AND UWB TRANSMISSION METHOD 有权
标题翻译： UWB传输设备和UWB传输方法
公开(公告)号：US20100166037A1
公开(公告)日：2010-07-01
申请号：US12377113
申请日：2007-10-10
申请人： Lei Soo Huang , Ping Luo , Suguru Fujita , Kazuaki Takahashi
发明人： Lei Soo Huang , Ping Luo , Suguru Fujita , Kazuaki Takahashi
IPC分类号： H04B1/69
CPC分类号： H04L27/0008 , H04B1/7176 , H04L27/02 , H04L27/18
摘要： A UWB transmission apparatus that, in a system using a mixture of amplitude and phase modulation schemes, can support both of the amplitude and phase modulation schemes, while preventing the signal powers of amplitude-modulated signals from degrading. In this UWB transmission apparatus, if the modulation mode is of QPSK, a mapping part (121) selects one of four signal points on the IQ plane in accordance with a 2-bit data, and outputs information related to the I- and Q-components of the selected signal point to a QPSK/ASK modulated signal forming part (122). If the modulation mode is of ASK, the mapping part (121) selects the origin point on the IQ plane when the data being ‘0’ and selects one of four signal points on the IQ plane, similarly to the case of QPSK modulation, when the data being ‘1,’ and outputs information, which is related to the selected signal point, to the QPSK/ASK modulated signal forming part (122).
摘要翻译：一种UWB传输装置，其在使用幅度和相位调制方案的混合的系统中可以支持幅度和相位调制方案两者，同时防止幅度调制信号的信号功率降级。在该UWB发送装置中，如果调制模式为QPSK，则映射部（121）根据2比特数据选择IQ平面上的四个信号点中的一个，并且输出与I和Q- 所选信号的分量指向QPSK / ASK调制信号形成部分（122）。如果调制方式为ASK，映射部分（121）在数据为“0”时选择IQ平面上的原点，并选择IQ平面上的四个信号点中的一个，类似于QPSK调制的情况，当数据为“1”，并将与所选信号点相关的信息输出到QPSK / ASK调制信号形成部分（122）。

10. 发明授权

US07706452B2 Reception device, transmission device, and radio system 有权
标题翻译：接收设备，传输设备和无线电系统
公开(公告)号：US07706452B2
公开(公告)日：2010-04-27
申请号：US10599378
申请日：2005-03-15
申请人： Suguru Fujita , Kazuaki Takahashi , Masahiro Mimura
发明人： Suguru Fujita , Kazuaki Takahashi , Masahiro Mimura
IPC分类号： H04L27/00
CPC分类号： H04B1/7174 , G01S13/931 , H04B1/71632 , H04B1/71637 , H04B1/719
摘要： A transmitter using a plurality of pulse signals having different pulse sequence times, a receiver for steadily demodulating pulse signals of only desirable wave, and a wireless system are disclosed. In the transmitter, a control signal generating circuit outputs a control signal for generating a plurality of pulse signals having different pulse sequence generating times, a pulse generating circuit generates a plurality of pulse signals by using the control signal. In the receiver, reception front end receives the plurality of pulse signals having different pulse sequence generating times, delay circuit delays at least one of reception front-end output signals supplied from the reception front-end by a given time, delay pulse composition circuit combines delay signal with reception front-end output signal, so that the receiver steadily demodulates the pulse signals of only the desirable wave.
摘要翻译：公开了使用具有不同脉冲序列时间的多个脉冲信号的发射机，用于稳定地解调仅期望波的脉冲信号的接收机和无线系统。在发送器中，控制信号发生电路输出用于产生具有不同脉冲序列产生时间的多个脉冲信号的控制信号，脉冲发生电路通过使用控制信号产生多个脉冲信号。在接收机中，接收前端接收具有不同脉冲序列产生时间的多个脉冲信号，延迟电路将从接收前端提供的接收前端输出信号中的至少一个延迟给定时间，延迟脉冲合成电路组合具有接收前端输出信号的延迟信号，使得接收机稳定地解调仅需要的波的脉冲信号。

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