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31. 发明授权

US07804122B2 Non-volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07804122B2
公开(公告)日：2010-09-28
申请号：US12434828
申请日：2009-05-04
申请人： Chin-Hsien Chen , Ying-Tso Chen , Chien-Hung Liu , Shou-Wei Huang
发明人： Chin-Hsien Chen , Ying-Tso Chen , Chien-Hung Liu , Shou-Wei Huang
IPC分类号： H01L31/119
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer.
摘要翻译：非易失性存储器包括具有两个开口的衬底，设置在两个开口之间的衬底上的堆叠栅极结构，设置在两个开口中的每一个的底部和两个开口中的每一个的侧壁的一部分的衬垫，设置在两个开口中的每一个的底部的衬垫上的第二导电层，以及在第二导电层和衬垫上的第三导电层。层叠栅极结构包括第一介电层，电荷存储层，第二介电层和第一导电层。衬垫具有比衬底更低的顶表面。第二导电层具有与衬垫的顶表面共面的顶表面。第三导电层具有至少与基底的共面的顶表面，并且低于第一介电层的顶表面。

32. 发明申请

US20100055843A1 CHIP PACKAGE MODULE HEAT SINK 审中-公开
标题翻译：芯片封装模块散热片
公开(公告)号：US20100055843A1
公开(公告)日：2010-03-04
申请号：US12615159
申请日：2009-11-09
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： H01L21/00
CPC分类号： H01L23/3677 , H01L23/3114 , H01L2924/0002 , H01L2924/00
摘要： A heat sink mechanism including multiple heat passages in the base of a casing of a chip package module penetrating through a substrate packed in the module; a metal material being deposited in each heat passage to become a heat sink conductor connecting the substrate and the surface of the casing to effectively solve the problem of excessive heat generated in the course of HF operation of the chip package module thus to prevent chip failure.
摘要翻译：一种散热机构，包括穿过包装在所述模块中的基板的芯片封装模块的壳体的底部中的多个热通道; 沉积在每个热通道中的金属材料成为连接衬底和壳体表面的散热导体，以有效地解决芯片封装模块的HF操作过程中产生的过多热量的问题，从而防止芯片故障。

33. 发明申请

US20080054322A1 MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：内存及其制造方法
公开(公告)号：US20080054322A1
公开(公告)日：2008-03-06
申请号：US11468311
申请日：2006-08-30
申请人： Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen , Yu-Tsung Lin
发明人： Chien-Hung Liu , Shou-Wei Huang , Ying-Tso Chen , Yu-Tsung Lin
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11568
摘要： A memory is provided. The memory includes a substrate, a number of parallel bit lines, a number of parallel word lines and at least a oxide-nitride-oxide (ONO) structure. The bit lines are disposed in the substrate. The word lines are disposed on the substrate. The word lines are crossed with but not perpendicular to the bit lines. The ONO structure is disposed between the word lines and the substrate.
摘要翻译：提供记忆。存储器包括衬底，多个并行位线，多个并行字线和至少氧化物 - 氧化物 - 氧化物（ONO）结构。位线设置在基板中。字线设置在基板上。字线与位线交叉但不垂直于位线。 ONO结构设置在字线和衬底之间。

34. 发明申请

US20070117322A1 Method for fabricating NAND type dual bit nitride read only memory 有权
公开(公告)号：US20070117322A1
公开(公告)日：2007-05-24
申请号：US11655259
申请日：2007-01-19
申请人： Chien-Hung Liu
发明人： Chien-Hung Liu
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/513 , H01L29/518 , H01L29/7923
摘要： A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

35. 发明授权

US06787416B2 Non volatile embedded memory with poly protection layer 有权
标题翻译：非易失性嵌入式存储器，具有多层保护层
公开(公告)号：US06787416B2
公开(公告)日：2004-09-07
申请号：US10253039
申请日：2002-09-24
申请人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Hung
发明人： Tung-Cheng Kuo , Chien-Hung Liu , Shyi-Shuh Pan , Shou-Wei Hung
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.
摘要翻译：本发明包括用于形成非易失性存储器单元和外围设备的装置和方法，对电子俘获层的损害降低，并且可选地在CMOS处理期间减少热暴露。在权利要求书，说明书和附图中描述了本发明的特定方面。

36. 发明授权

US06559010B1 Method for forming embedded non-volatile memory 有权
标题翻译：嵌入式非易失性存储器的形成方法
公开(公告)号：US06559010B1
公开(公告)日：2003-05-06
申请号：US10003320
申请日：2001-12-06
申请人： Tung-Cheng Kuo , Shou-Wei Hwang , Chien-Hung Liu , Shyi-Shuh Pan
发明人： Tung-Cheng Kuo , Shou-Wei Hwang , Chien-Hung Liu , Shyi-Shuh Pan
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.
摘要翻译：描述了一种用于形成非易失性存储器的方法，包括将衬底划分成至少存储器阵列区域和逻辑器件区域。首先在衬底上形成氧化物/氮化物/氧化物（ONO）层，并且通过位线光刻工艺在ONO层上形成光致抗蚀剂层，并在衬底上进行位线离子注入工艺以形成多个位线结构。然后，通过字线照片条件沉积第一多晶硅层以形成多个字线。互补金属氧化物半导体（CMOS）ONO层用于存储电荷，并且ONO层仅被光致抗蚀剂层触及一次。此外，存储器阵列区域和逻辑器件区域的分离的调整照相条件可以产生安全的氧化物厚度，以通过使用自对准硅化物处理来解决位线到位线之间的泄漏路径的问题。

37. 发明授权

US06440798B1 Method of forming a mixed-signal circuit embedded NROM memory and MROM memory 有权
标题翻译：形成嵌入式NROM存储器和MROM存储器的混合信号电路的方法
公开(公告)号：US06440798B1
公开(公告)日：2002-08-27
申请号：US09682148
申请日：2001-07-26
申请人： Erh-Kun Lai , Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan , Ying-Tso Chen
发明人： Erh-Kun Lai , Chien-Hung Liu , Shou-Wei Huang , Shyi-Shuh Pan , Ying-Tso Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： The present invention gives a method for creating a NROM memory from a semiconductor substrate. Numerous process steps are included to achieve this including forming shallow trench isolation areas, many ion implantation processes, ROM code implantation processes, photolithography and creation of layers and removal of layers. At the end of the process a mixed-signal circuit embedded NROM and NROM memory are created.
摘要翻译：本发明提供了一种从半导体衬底生成NROM存储器的方法。包括许多工艺步骤以实现这一点，包括形成浅沟槽隔离区域，许多离子注入工艺，ROM代码注入工艺，光刻以及层的创建和层的去除。在该过程结束时，创建了嵌入NROM和NROM存储器的混合信号电路。

38. 发明授权

US09088206B2 Power module and the method of packaging the same 有权
标题翻译：电源模块及其封装方法相同
公开(公告)号：US09088206B2
公开(公告)日：2015-07-21
申请号：US13359466
申请日：2012-01-26
申请人： Ho-Yin Yiu , Chien-Hung Liu , Wei-Chung Yang , Bai-Yao Lou
发明人： Ho-Yin Yiu , Chien-Hung Liu , Wei-Chung Yang , Bai-Yao Lou
IPC分类号： H01L29/06 , H01L27/06 , H04B1/02 , H02M3/155 , H02M3/00 , H01F17/00 , H01L23/64 , H01L25/16 , H01L23/00 , H01L25/07
CPC分类号： H02M3/155 , H01F17/0006 , H01F2017/0046 , H01F2017/0073 , H01F2017/0086 , H01L23/645 , H01L24/16 , H01L25/072 , H01L25/165 , H01L2224/16225 , H01L2924/13091 , H01L2924/16195 , H01L2924/19105 , H02M3/00
摘要： A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.
摘要翻译：电源模块包括基板; 形成在具有特定图案的基板上的导电路径层作为电感器; 连接层形成在所述基板上并电连接到所述电感器的第一端子; 以及第一晶体管，通过连接层电安装在基板上。

39. 发明授权

US08981497B2 Chip package structure and method for forming the same 有权
标题翻译：芯片封装结构及其形成方法
公开(公告)号：US08981497B2
公开(公告)日：2015-03-17
申请号：US13548663
申请日：2012-07-13
申请人： Ho-Yin Yiu , Chien-Hung Liu , Tsang-Yu Liu , Ying-Nan Wen , Yen-Shih Ho
发明人： Ho-Yin Yiu , Chien-Hung Liu , Tsang-Yu Liu , Ying-Nan Wen , Yen-Shih Ho
IPC分类号： H01L27/14 , H01L29/82 , H01L29/84 , B81B3/00 , H01L27/146
CPC分类号： B81B3/0051 , B81B2201/025 , H01L27/14618 , H01L2924/0002 , H01L2924/00
摘要： A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.
摘要翻译：公开了一种用于形成芯片封装结构的芯片封装结构和方法。至少一个块形成在盖的表面上，盖安装在其上形成有感测装置的基板上，用于覆盖感测装置，并且该块设置在盖和感测装置之间。在本发明中，该块安装在盖上，不需要蚀刻盖以形成突出部分，因此本发明的方法简单且成本低。

40. 发明授权

US08791768B2 Capacitive coupler packaging structure 有权
标题翻译：电容耦合器封装结构
公开(公告)号：US08791768B2
公开(公告)日：2014-07-29
申请号：US13359460
申请日：2012-01-26
申请人： Ho-Yin Yiu , Chien-Hung Liu , Ying-Nan Wen , Shih-Yi Lee , Wei-Chung Yang , Bai-Yao Lou , Hung-Jen Lee
发明人： Ho-Yin Yiu , Chien-Hung Liu , Ying-Nan Wen , Shih-Yi Lee , Wei-Chung Yang , Bai-Yao Lou , Hung-Jen Lee
IPC分类号： H01P5/08 , H05K1/18
CPC分类号： H01L23/642 , H01L23/48 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/13101 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/01327 , H01L2924/1901 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/014
摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.
摘要翻译：本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间，并且第一电极层通过焊球电连接到接收器。电容耦合器封装结构还包括电连接到电容器的发射器。

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