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31. 发明申请

US20080064165A1 DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US20080064165A1
公开(公告)日：2008-03-13
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

32. 发明授权

US07294573B1 Method for controlling poly 1 thickness and uniformity in a memory array fabrication process 有权
标题翻译：用于控制存储器阵列制造工艺中聚1厚度和均匀性的方法
公开(公告)号：US07294573B1
公开(公告)日：2007-11-13
申请号：US11035188
申请日：2005-01-13
申请人： Krishnashree Achuthan , Unsoon Kim , Kashmir Sahota , Patriz C. Regalado
发明人： Krishnashree Achuthan , Unsoon Kim , Kashmir Sahota , Patriz C. Regalado
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7684
摘要： According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.
摘要翻译：根据一个示例性实施例，一种方法包括将位于衬底上的场氧化物区域上的多晶硅层平坦化以形成多晶硅段，其中多晶硅段具有与场氧化物区域的顶表面基本上平面的顶表面，场氧化物区域具有第一高度，并且多晶硅段具有第一厚度。该方法还包括在衬底的周边区域上去除硬掩模。根据该示例性实施例，该方法还包括蚀刻多晶硅段以使多晶硅段具有第二厚度，这导致多晶硅段的顶表面位于场氧化物区的顶表面之下。可以通过使用湿蚀刻工艺来蚀刻多晶硅段。多晶硅段位于衬底的芯区域中。

33. 发明授权

US07078314B1 Memory device having improved periphery and core isolation 失效
标题翻译：具有改进的外围和核心隔离的存储器件
公开(公告)号：US07078314B1
公开(公告)日：2006-07-18
申请号：US10407999
申请日：2003-04-03
申请人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun
发明人： Unsoon Kim , Hiroyuki Kinoshita , Yu Sun
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/1052
摘要： The present invention discloses a memory device having an improved periphery isolation region and core isolation region. A first trench is formed in a core region. Substrate material bordering the first trench is then oxidized to form a first liner. The first liner is then removed. A second trench is then formed in a periphery region. A second oxidation is then performed such that a second liner is formed from the substrate material bordering the first and second trenches. A dielectric trench fill having substantially uniform density is then deposited in the first and second trenches.
摘要翻译：本发明公开了一种具有改进的外围隔离区域和核心隔离区域的存储器件。第一沟槽形成在芯区域中。然后与第一沟槽接壤的衬底材料被氧化以形成第一衬里。然后将第一个衬垫取出。然后在周边区域中形成第二沟槽。然后执行第二氧化，使得第二衬垫由与第一和第二沟槽接壤的衬底材料形成。然后在第一和第二沟槽中沉积具有基本均匀密度的电介质沟槽填料。

34. 发明授权

US06670691B1 Shallow trench isolation fill process 有权
标题翻译：浅沟隔离填充过程
公开(公告)号：US06670691B1
公开(公告)日：2003-12-30
申请号：US10174550
申请日：2002-06-18
申请人： Harpreet K. Sachar , Unsoon Kim , Jack F. Thomas
发明人： Harpreet K. Sachar , Unsoon Kim , Jack F. Thomas
IPC分类号： H01L2900
CPC分类号： H01L21/76229
摘要： A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.
摘要翻译：公开了一种用于在半导体制造工艺期间填充窄隔离沟槽的方法。半导体包括形成在基板的芯区域中的高纵横比窄隔离沟槽和形成在基板的电路区域中的宽隔离沟槽。在沟槽形成之后，在其中生长热氧化层的厚度足以完全填充高纵横比窄隔离沟槽的所有隔离沟槽中进行厚衬层氧化。在衬里氧化之后，宽隔离沟槽填充有隔离电介质，由此所有沟槽均匀地填充有最小的空隙。

35. 发明授权

US06555867B1 Flash memory gate coupling using HSG polysilicon 失效
标题翻译：使用HSG多晶硅的闪存栅极耦合
公开(公告)号：US06555867B1
公开(公告)日：2003-04-29
申请号：US08991448
申请日：1997-12-16
申请人： Unsoon Kim
发明人： Unsoon Kim
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/0207 , H01L27/115 , H01L27/11519 , H01L29/4925
摘要： A method for improving the gate coupling in a flash memory core includes forming floating gates of memory element stacks by depositing a first polysilicon layer having relatively small grain size on a tunnel oxide layer and then depositing a second polysilicon layer on the first, the second polysilicon layer being made of relatively large hemispherical-grained (HSG) polysilicon crystals, which improves gate coupling. In contrast, owing to the relatively small size of its grains, the first layer of polysilicon advantageously establishes a relatively flat surface interface with the tunnel oxide layer that is between the memory stacks and the underlying silicon substrate. Conventional control gates are then established above the HSG layer.
摘要翻译：一种用于改善闪速存储器芯中的栅极耦合的方法包括：通过在隧道氧化物层上沉积具有相对较小晶粒尺寸的第一多晶硅层，然后在第一多晶硅层上沉积第二多晶硅层，形成存储元件堆叠的浮置栅极层由相对大的半球形（HSG）多晶硅晶体制成，这改善了栅极耦合。相反，由于其晶粒的尺寸相对较小，所以第一层多晶硅有利地建立了与存储堆和底层硅衬底之间的隧道氧化物层相对平坦的表面界面。然后在HSG层之上建立传统的控制门。

36. 发明授权

US5981341A Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core 失效
标题翻译：用于在自对准闪存芯内隔离沟槽形成期间保护隧道氧化物的侧壁间隔物
公开(公告)号：US5981341A
公开(公告)日：1999-11-09
申请号：US986160
申请日：1997-12-05
申请人： Unsoon Kim , Yowjuang W. Liu , Yu Sun , Angela T. Hui
发明人： Unsoon Kim , Yowjuang W. Liu , Yu Sun , Angela T. Hui
IPC分类号： H01L21/762 , H01L21/8247 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76224
摘要： A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks, to thereby shield the tunnel oxide during isolation trench etching.
摘要翻译：用于制造自对准隔离闪存芯的方法，而不损坏存储元件堆叠和支撑堆叠的硅衬底之间的隧道氧化物层，包括在蚀刻堆叠之间的隔离沟槽之前在堆叠上沉积三个侧壁层，从而屏蔽隔离沟槽蚀刻期间的隧道氧化物。

37. 发明授权

US07985687B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US07985687B1
公开(公告)日：2011-07-26
申请号：US11186969
申请日：2005-07-22
申请人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
发明人： Angela T. Hui , Hiroyuki Kinoshita , Unsoon Kim , Harpreet K. Sachar
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28273 , H01L21/28282 , H01L21/3081 , H01L21/31111 , H01L21/76232 , H01L27/11521 , H01L27/11568
摘要： A method for forming a memory device includes forming a hard mask over a substrate, where the hard mask includes a first mask layer and a second mask layer formed over the first mask layer. The substrate is etched to form a trench. The trench is filled with a field oxide material. The second mask layer is stripped from the memory device using a first etching technique and the first mask layer is stripped from the memory device using a second etching technique, where the second etching technique is different than the first etching technique.
摘要翻译：一种用于形成存储器件的方法包括在衬底上形成硬掩模，其中硬掩模包括形成在第一掩模层上的第一掩模层和第二掩模层。蚀刻衬底以形成沟槽。沟槽填充有场氧化物材料。使用第一蚀刻技术从存储器件剥离第二掩模层，并且使用第二蚀刻技术将第一掩模层从存储器件剥离，其中第二蚀刻技术不同于第一蚀刻技术。

38. 发明授权

US06764920B1 Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices 有权
标题翻译：用于使用偏氮化物带和用于高性能闪存器件的小鸟嘴形成来减少隧道氧化物上的浅沟槽隔离边缘薄化的方法
公开(公告)号：US06764920B1
公开(公告)日：2004-07-20
申请号：US10126840
申请日：2002-04-19
申请人： Nian Yang , John Jianshi Wang , Unsoon Kim
发明人： Nian Yang , John Jianshi Wang , Unsoon Kim
IPC分类号： H01L2176
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L21/823481 , H01L29/66825
摘要： A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides (510) for flash memories (devices M and N). An STI process is implemented to isolate flash memory devices (devices M and N) in the semiconductor structure (200). In the STI process, a nitride layer (210) is deposited over a silicon substrate (280). An STI region (290) is formed defining STI corners (240) where a top surface (270) of the silicon substrate (280) and the STI region (290) converge. The STI region (290) is filled with an STI field oxide and planarized until reaching the nitride layer (210). A local oxidation of silicon (LOCOS) is then performed to oxidize the top surface (270) of the silicon substrate adjacent to the STI corners (240). Oxidized silicon is grown to boost the thickness of a later formed tunnel oxide layer (510) at the STI corners (240).
摘要翻译：一种半导体集成电路制造方法。具体地，本发明的一个实施例公开了一种用于减少硅的浅沟槽隔离（STI）角凹槽的方法，以便减少闪存（器件M和N）的隧道氧化物（510）上的STI边缘变薄。实施STI处理以隔离半导体结构（200）中的闪存器件（器件M和N）。在STI工艺中，氮化物层（210）沉积在硅衬底（280）上。形成STI区域（290），其限定了硅基板（280）的顶表面（270）和STI区域（290）会聚的STI拐角（240）。 STI区域（290）填充有STI场氧化物并且被平坦化直到到达氮化物层（210）。然后进行硅的局部氧化（LOCOS）以氧化邻近STI拐角（240）的硅衬底的顶表面（270）。生长氧化硅以增强在STI拐角（240）处的稍后形成的隧道氧化物层（510）的厚度。

39. 发明授权

US6103593A Method and system for providing a contact on a semiconductor device 失效
标题翻译：用于在半导体器件上提供接触的方法和系统
公开(公告)号：US6103593A
公开(公告)日：2000-08-15
申请号：US23836
申请日：1998-02-13
申请人： Angela T. Hui , Hung-Sheng Chen , Unsoon Kim
发明人： Angela T. Hui , Hung-Sheng Chen , Unsoon Kim
IPC分类号： H01L21/762 , H01L21/768 , H01L21/76 , H01L21/44
CPC分类号： H01L21/76802 , H01L21/76237 , H01L21/76834 , Y10S438/97
摘要： A method for providing at least one contact on a semiconductor is disclosed. The semiconductor includes a plurality of isolation structures. The method and system include providing an etch-stop layer in direct contact with the semiconductor, providing a dielectric layer over the etch-stop layer, and etching through the dielectric layer and a portion of the etch-stop layer. A portion of the semiconductor in proximity with one of the plurality of isolation structures is not exposed during the etch.
摘要翻译：公开了一种在半导体上提供至少一个接触的方法。半导体包括多个隔离结构。该方法和系统包括提供与半导体直接接触的蚀刻停止层，在蚀刻停止层上方提供介电层，以及蚀刻穿过介电层和蚀刻停止层的一部分。在蚀刻期间，与多个隔离结构之一接近的半导体的一部分不暴露。

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