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31. 发明授权

US4142853A Process for improving cellulose fiber properties and for dyeing the same 失效
标题翻译：改善纤维素纤维性能并进行染色的方法
公开(公告)号：US4142853A
公开(公告)日：1979-03-06
申请号：US696709
申请日：1976-06-16
申请人： Yasuhiko Terada , Jun Yasuda , Masao Kuriyama
发明人： Yasuhiko Terada , Jun Yasuda , Masao Kuriyama
IPC分类号： D06P5/00 , D06M13/02 , D06M13/184 , D06M101/00 , D06M101/02 , D06M101/06 , D06M101/08 , D06P5/22 , D06P5/28 , D06M13/20
CPC分类号： D06P5/005 , D06M13/184 , D06P5/22
摘要： A process for improving the properties, particularly the dyeing properties, of cellulose fibers. The process comprises impregnating cellulose fiber with an aromatic acyl halide and thereafter immersing the impregnated fiber into an aqueous solution containing more than about 10% by weight of an alkali hydroxide to acylate the cellulose fiber on the surface portion thereof. In another embodiment of the invention, a continuous process for improving the properties of cellulose fiber yarn or fabric is provided. According to the continuous process, uniform acylation is achieved by maintaining the yarn or fabric in a stretched state during impregnation with the aromatic acyl halide and during the initial stages of immersion in the aqueous alkali hydroxide. The acylated cellulose fiber produced according to the invention may be dyed with good color fastness with disperse dyes and still retain the soft tactility characteristic of the fiber.
摘要翻译：用于改善纤维素纤维的性能，特别是染色性能的方法。该方法包括用芳族酰卤浸渍纤维素纤维，然后将浸渍的纤维浸入含有大于约10重量％的碱金属氢氧化物的水溶液中以在其表面部分上酰化纤维素纤维。在本发明的另一个实施方案中，提供了用于改善纤维素纤维纱线或织物的性能的连续方法。根据连续方法，通过在用芳族酰卤浸渍过程中和在浸入碱性氢氧化碱水溶液的初始阶段期间将纱线或织物保持在拉伸状态来实现均匀酰化。根据本发明生产的酰化纤维素纤维可以用分散染料染色，具有良好的色牢度，并且仍保留纤维的柔软的触感特性。

32. 发明授权

US07848160B2 Semiconductor storage device and method for operating the same 有权
标题翻译：半导体存储装置及其操作方法
公开(公告)号：US07848160B2
公开(公告)日：2010-12-07
申请号：US12333884
申请日：2008-12-12
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G11C7/22 , G11C16/06 , G11C7/02
CPC分类号： G11C7/18 , G11C7/12
摘要： A semiconductor storage device includes a plurality of memory cells connected to first and second column trees, and a sensing circuit reading data from the memory cells. The sensing circuit performing a read operation by electrically connecting the column tree, which is connected to a read-selected memory cell, to a sensing node and electrically connecting the column tree, which is connected to a non-selected memory cell, to a reference sensing line.
摘要翻译：半导体存储装置包括连接到第一和第二列树的多个存储单元，以及从存储单元读取数据的感测电路。感测电路通过将连接到读选择的存储单元的列树电连接到感测节点并将连接到未选择的存储器单元的列树电连接到参考电路来执行读取操作传感线。

33. 发明授权

US07714637B2 Negative potential discharge circuit and method thereof 有权
标题翻译：负电位放电电路及其方法
公开(公告)号：US07714637B2
公开(公告)日：2010-05-11
申请号：US11812927
申请日：2007-06-22
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G05F3/02
CPC分类号： G11C5/147 , G11C5/145 , G11C16/30
摘要： A negative potential discharge circuit may include an internal voltage generating circuit and/or a discharge unit. The internal voltage generating circuit may be configured to generate a regulated output voltage based on a power supply voltage. The discharge unit may be configured to discharge a negative potential using the regulated output voltage. A method of discharging a negative potential may include generating a regulated output voltage based on a power supply voltage, and/or discharging a negative potential using the regulated output voltage.
摘要翻译：负电位放电电路可以包括内部电压产生电路和/或放电单元。内部电压发生电路可以被配置为基于电源电压产生稳定的输出电压。放电单元可以被配置为使用调节的输出电压来放电负电位。放电负电位的方法可以包括基于电源电压产生稳定的输出电压，和/或使用调节的输出电压来排出负电位。

34. 发明授权

US07605643B2 Voltage generation circuit and method thereof 有权
标题翻译：电压产生电路及其方法
公开(公告)号：US07605643B2
公开(公告)日：2009-10-20
申请号：US11812682
申请日：2007-06-21
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A voltage generation circuit may include a static current circuit and/or a current mirror. The static current circuit may include a first resistor. The current mirror may include a second resistor, a third resistor, and/or an output terminal.
摘要翻译：电压产生电路可以包括静态电流电路和/或电流镜。静态电流电路可以包括第一电阻器。电流镜可以包括第二电阻器，第三电阻器和/或输出端子。

35. 发明申请

US20050117406A1 Semiconductor integrated circuit device with main cell array and fuse cell array 失效
标题翻译：具有主单元阵列和熔丝单元阵列的半导体集成电路器件
公开(公告)号：US20050117406A1
公开(公告)日：2005-06-02
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

36. 发明授权

US06711066B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06711066B2
公开(公告)日：2004-03-23
申请号：US10198170
申请日：2002-07-19
申请人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
发明人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
IPC分类号： G11C700
CPC分类号： G11C16/107 , G11C16/30 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3477
摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
摘要翻译：电位产生电路产生两种类型的擦除验证阈值EVT1和EVT2。这些值满足EVT2 = EVT1 +（OEVT-EVTL）的关系。 OEVT是过擦除验证阈值。当擦除验证阈值设定为EVT2时，数据擦除后阈值电压分布的下限高于OEVT。 EVTL是数据擦除后的阈值电压分布的下限，擦除验证阈值设定为EVT1，低于OEVT。根据操作模式切换擦除验证阈值EVT1和EVT2。在写入/擦除测试期间，例如，擦除验证阈值被设置为EVT2。另一方面，在正常操作期间，将擦除验证阈值设置为EVT1。

37. 发明授权

US06480427B2 Negative-potential detecting circuit having an enhanced sensitivity of detecting negative potentials 有权
公开(公告)号：US06480427B2
公开(公告)日：2002-11-12
申请号：US09789712
申请日：2001-02-22
申请人： Masao Kuriyama
发明人： Masao Kuriyama
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C16/06
摘要： A negative-potential detecting circuit includes first and second resistance elements connected in series between an output end of a constant-current source for outputting a constant current and a negative-potential node for generating a negative potential, a third resistance element connected between a connection node between the first and second resistance elements and a fixed-potential node, and a comparator for comparing a potential of a connection node between the constant-current source and the first resistance element and a reference potential with each other. The comparator detects a level of a negative potential by comparing the potential of the connection node and the reference potential.

38. 发明授权

US06442080B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US06442080B2
公开(公告)日：2002-08-27
申请号：US09812572
申请日：2001-03-21
申请人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
发明人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
IPC分类号： G11C1140
CPC分类号： G11C16/107 , G11C16/30 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3477
摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
摘要翻译：电位产生电路产生两种类型的擦除验证阈值EVT1和EVT2。这些值满足EVT2 = EVT1 +（OEVT-EVTL）的关系。 OEVT是过擦除验证阈值。当擦除验证阈值设定为EVT2时，数据擦除后阈值电压分布的下限高于OEVT。 EVTL是数据擦除后的阈值电压分布的下限，擦除验证阈值设定为EVT1，低于OEVT。根据操作模式切换擦除验证阈值EVT1和EVT2。在写入/擦除测试期间，例如，擦除验证阈值被设置为EVT2。另一方面，在正常操作期间，将擦除验证阈值设置为EVT1。

39. 发明授权

US5568419A Non-volatile semiconductor memory device and data erasing method therefor 失效
标题翻译：非挥发性半导体存储器件及其数据擦除方法
公开(公告)号：US5568419A
公开(公告)日：1996-10-22
申请号：US507968
申请日：1995-07-27
申请人： Shigeru Atsumi , Masao Kuriyama , Hironori Banba , Akira Umezawa , Nobuaki Otsuka
发明人： Shigeru Atsumi , Masao Kuriyama , Hironori Banba , Akira Umezawa , Nobuaki Otsuka
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/3445
摘要： A memory cell array has a plurality of memory cells formed of EEPROM cells arranged in a matrix form. Data in the memory cells is flash-erased, and after this, word lines other than a selected word line are set to a negative potential and erasing verification for detecting an insufficiently erased memory cell is effected. The flash-erasing and erasing verification are repeatedly effected until no insufficiently erased memory cell is detected. When no insufficiently erased memory cell is detected, word lines other than a selected word line are set to a negative potential and an overerased memory cell is detected. When an overerased memory cell is detected, weak program is effected for the cell by applying a voltage lower than the normal writing voltage to the cell.
摘要翻译：存储单元阵列具有以矩阵形式布置的EEPROM单元形成的多个存储单元。存储器单元中的数据被闪存擦除，之后，除了所选字线之外的字线被设置为负电位，并且实现用于检测不充分擦除的存储器单元的擦除验证。重复进行闪光擦除和擦除验证，直到没有检测到不充分擦除的存储单元。当没有检测到不充分擦除的存储单元时，除了所选字线以外的字线被设置为负电位，并且检测到过高的存储单元。当检测到过高的存储单元时，通过将低于正常写入电压的电压施加到单元来对单元进行弱程序。

40. 发明授权

US5259013A Hard x-ray magnification apparatus and method with submicrometer spatial resolution of images in more than one dimension 失效
标题翻译：硬X射线放大装置和方法，具有亚微米尺度多维图像中的空间分辨率
公开(公告)号：US5259013A
公开(公告)日：1993-11-02
申请号：US808850
申请日：1991-12-17
申请人： Masao Kuriyama , Ronald C. Dobbyn , Richard D. Spal
发明人： Masao Kuriyama , Ronald C. Dobbyn , Richard D. Spal
IPC分类号： G21K1/06 , G21K7/00
CPC分类号： G21K1/06 , G21K7/00
摘要： An apparatus and a method are provided for employing hard monochromatic x-rays to generate high resolution, dimensionally altered undistorted images of either the internal structure or surface feature details of a specimen at the submicron level in up to three-dimensions. A monochromatic hard x-ray beam is applied to the specimen and thereafter is directed to arrive at a small angle of incidence at a preferably flat, optically polished surface of a nearly perfect crystal, to be diffracted at the surface thereof to carry a first one-dimensional alteration of the image of the observed structure of the specimen. This x-ray beam is then directed, at a small angle of incidence, to the surface of a second nearly perfect crystal, the receiving surface being oriented orthogonal to the surface of the first nearly perfect crystal, to generate a further diffracted beam containing an undistorted two-dimensionally altered inverted image of the specimen with micrometer spatial resolution. The "magnification factor" of the same set of highly-perfect crystals can be varied by zooming by changing the x-ray energy of the incident beam. This last beam is received on a CCD array for direct conversion of x-ray photons into electrical charges and storage and processing of the resultant data in digitized form. By a small controlled rotation to the specimen relative to the apparatus, additional two-dimensional data are obtained and may be processed to generate high resolution three-dimensional images of the specimen structure.
摘要翻译：提供了一种装置和方法，用于使用硬单色x射线以最多三维的方式在亚微米级别产生样品的内部结构或表面特征细节的高分辨率，尺寸改变的未失真图像。将单色硬x射线束施加到样本上，然后被引导到在几乎完美的晶体的优选平坦的，光学抛光的表面上以小的入射角度到达，以在其表面衍射以携带第一个观察到的样本结构的图像的维度改变。然后将该X射线束以小的入射角被引导到第二接近完美晶体的表面，接收表面定向成与第一近似完美的晶体的表面正交，以产生另外的衍射光束，其包含用千分尺空间分辨率进行未失真的二维改变的样本倒置图像。通过改变入射光束的X射线能量，可以通过变焦来改变同一组高度完美的晶体的“放大系数”。该最后一个光束被接收在CCD阵列上，用于将x射线光子直接转换成电荷并以数字形式存储和处理所得数据。通过相对于装置对样本的小的受控旋转，获得额外的二维数据，并且可以处理以产生样本结构的高分辨率三维图像。

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