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31. 发明授权

US07399678B2 Method for reading an array of multi-bit ROM cells with each cell having bi-directional read 有权
标题翻译：用于读取具有双向读取的每个单元的多位ROM单元阵列的方法
公开(公告)号：US07399678B2
公开(公告)日：2008-07-15
申请号：US11292557
申请日：2005-12-02
申请人： Dana Lee , Bomy Chen
发明人： Dana Lee , Bomy Chen
IPC分类号： H01L21/8234
CPC分类号： H01L27/11266 , G11C11/5692 , G11C17/12 , H01L27/112
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。门间隔开并与通道的至少第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

32. 发明授权

US07307308B2 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation 有权
标题翻译：埋入位线非挥发性浮动栅极存储单元，其具有沟槽中的独立可控制控制栅极及其阵列，以及形成方法
公开(公告)号：US07307308B2
公开(公告)日：2007-12-11
申请号：US10797296
申请日：2004-03-09
申请人： Dana Lee , Bomy Chen , Sohrab Kianian
发明人： Dana Lee , Bomy Chen , Sohrab Kianian
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C16/0458 , G11C16/0483 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L29/42336
摘要： A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.
摘要翻译：掩埋位线读/程序非易失性存储单元和阵列能够实现高密度。电池和阵列由具有多个间隔开的沟槽的半导体衬底制成，沟槽之间具有平坦表面。每个沟槽都有一个侧壁和一个底壁。每个存储单元具有用于存储其上的电荷的浮动栅极。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有两个部分。源/漏区中的一个位于沟槽的底壁。浮动栅极在沟槽中，并且在沟槽的第一部分之上并且与沟槽的侧壁间隔开。栅电极控制在衬底的平面中的第二部分中的沟道的导通。另一个源极/漏极区域位于衬底的平面表面中的衬底中。独立可控的控制栅极也在沟槽中，与浮动栅极绝缘并且与其电容耦合。通过热通道电子注入的电池程序，并且通过Fowler-Nordheim将电子从浮栅隧穿到栅电极或从浮栅到沟槽底壁处的源极/漏极区擦除。源极，漏极和控制栅极都基本上彼此平行，栅电极基本上垂直于源极/漏极/控制栅极。源极/漏极线被埋在衬底中，形成虚拟接地阵列。

33. 发明申请

US20070210369A1 Single gate-non-volatile flash memory cell 审中-公开
标题翻译：单门非易失性闪存单元
公开(公告)号：US20070210369A1
公开(公告)日：2007-09-13
申请号：US11375386
申请日：2006-03-13
申请人： Bomy Chen , Yaw Hu , Dana Lee
发明人： Bomy Chen , Yaw Hu , Dana Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324
摘要： A non-volatile floating gate memory cell, having a single polysilicon gate, compatible with conventional logic processes, comprises a substrate of a first conductivity type. A first and a second region of a second conductivity type are in the substrate, spaced apart from one another to define a channel region therebetween. A first gate is insulated from the substrate and is positioned over a first portion of the channel region and over the first region and is substantially capacitively coupled thereto. A second gate is insulated from the substrate, and is spaced apart from the first gate and is positioned over a second portion of the channel region, different from the first portion, and has little or no overlap with the second region.
摘要翻译：具有与常规逻辑处理兼容的单个多晶硅栅极的非易失性浮动栅极存储单元包括第一导电类型的衬底。第二导电类型的第一和第二区域在衬底中，彼此间隔开以限定它们之间的沟道区域。第一栅极与衬底绝缘并且被定位在沟道区域的第一部分上方并且超过第一区域并且基本上电容耦合到其上。第二栅极与衬底绝缘，并且与第一栅极间隔开并且位于与第一部分不同的沟道区域的第二部分上方，并且与第二区域几乎没有或没有重叠。

34. 发明授权

US07242050B2 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US07242050B2
公开(公告)日：2007-07-10
申请号：US10714243
申请日：2003-11-13
申请人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
发明人： Bomy Chen , Hieu Van Tran , Dana Lee , Jack Edward Frayer
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

35. 发明申请

US20070069275A1 Bi-directional read/program non-volatile floating gate memory array, and method of formation 有权
标题翻译：双向读/写非挥发性浮栅存储器阵列及其形成方法
公开(公告)号：US20070069275A1
公开(公告)日：2007-03-29
申请号：US11239791
申请日：2005-09-29
申请人： Felix Tsui , Jeng-Wei Yang , Bomy Chen , Chun-Ming Chen , Dana Lee , Changyuan Chen
发明人： Felix Tsui , Jeng-Wei Yang , Bomy Chen , Chun-Ming Chen , Dana Lee , Changyuan Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336
摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.
摘要翻译：双向读/写非易失性存储单元和阵列能够实现高密度。每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。双向读取允许将单元编程为存储位，每个浮动栅极中有一位。这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

36. 发明授权

US07183163B2 Method of manufacturing an isolation-less, contact-less array of bi-directional read/program non-volatile floating gate memory cells with independent controllable control gates 有权
标题翻译：制造具有独立可控制控制门的双向读/非易失性浮动栅极存储单元的无隔离，无接触阵列的方法
公开(公告)号：US07183163B2
公开(公告)日：2007-02-27
申请号：US10824016
申请日：2004-04-13
申请人： Dana Lee , Bomy Chen
发明人： Dana Lee , Bomy Chen
IPC分类号： H01L29/788 , H01L21/8238 , H01L21/336
CPC分类号： G11C16/0458 , G11C16/0483 , G11C16/0491 , H01L27/11521 , H01L29/42328 , H01L29/42336
摘要： A method of making an isolation-less, contact-less array of bi-directional read/program non-volatile memory cells is disclosed. Each memory cell has two stacked gate floating gate transistors, with a switch transistor there between. The source/drain lines of the cells and the control gate lines of the stacked gate floating gate transistors in the same column are connected together. The gate of the switch transistors in the same row are connected together. Spaced apart trenches are formed in a substrate in a first direction. Floating gates are formed in the trenches, along the side wall of the trenches. A buried source/bit line is formed at the bottom of each trench. A control gate common to both floating gates is also formed in each trench insulated from the floating gates, capacitively coupled thereto, and insulated from the buried source/bit line. Transistor gates parallel to one another are formed in a second direction, substantially perpendicular to the first direction on the planar surface of the substrate. In one embodiment, openings between the rows of transistor gates are used to cut the floating gates in the trenches, without cutting the control gates.
摘要翻译：公开了制造双向读/程序非易失性存储单元的无隔离，无接触阵列的方法。每个存储单元具有两个堆叠栅极浮栅晶体管，其间具有开关晶体管。单元的源极/漏极线和同一列中的堆叠栅极浮置栅极晶体管的控制栅极线连接在一起。同一行的开关晶体管的栅极连接在一起。在第一方向上在基板上形成间隔开的沟槽。沿着沟槽的侧壁在沟槽中形成浮动栅极。在每个沟槽的底部形成埋入的源极/位线。两个浮动栅极共用的控制栅极也形成在与浮动栅极绝缘的每个沟槽中，电容耦合到该栅极并且与掩埋源极/位线绝缘。在彼此平行的晶体管栅极形成在基板的平坦表面上基本上垂直于第一方向的第二方向上。在一个实施例中，晶体管栅极行之间的开口用于切割沟槽中的浮动栅极而不切断控制栅极。

37. 发明授权

US07119396B2 NROM device 有权
标题翻译： NROM设备
公开(公告)号：US07119396B2
公开(公告)日：2006-10-10
申请号：US10962008
申请日：2004-10-08
申请人： Bomy Chen , Dana Lee , Yaw Wen Hu , Bing Yeh
发明人： Bomy Chen , Dana Lee , Yaw Wen Hu , Bing Yeh
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11568 , H01L29/66553
摘要： A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.
摘要翻译：一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸，电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

38. 发明申请

US20060071255A1 Non-destructive read ferroelectric memory cell, array and integrated circuit device 审中-公开
标题翻译：非破坏性读铁电存储单元，阵列和集成电路器件
公开(公告)号：US20060071255A1
公开(公告)日：2006-04-06
申请号：US10949778
申请日：2004-09-24
申请人： Bomy Chen , Dana Lee , June Han
发明人： Bomy Chen , Dana Lee , June Han
IPC分类号： H01L29/94
CPC分类号： H01L27/11507 , G11C11/22 , G11C11/221 , H01L27/11502 , H01L28/55
摘要： A ferroelectric memory cell has a semiconductor substrate of a first conductivity type having a first region and a second region with each being of a second conductivity type, with a channel region therebetween. The first region and the second region are aligned in a first direction. A gate dielectric is over at least a portion of the channel region. A gate is over the gate dielectric, with the gate extending in a direction transverse to the first direction termination at a termination point not overlapping the first region, the second region and the channel region. A ferroelectric capacitor is at the termination point. The ferroelectric capacitor has a first end and a second end with the first end connected to the gate. The ferroelectric memory cell has three terminals: the first region, the second region, and the second end. In another embodiment, an insulator is over at least a portion of the first region. The gate has one end over the gate dielectric and extends over the insulator terminating at a termination point. A ferroelectric capacitor is connected to the termination point, which lies over a portion of the first region.
摘要翻译：铁电存储单元具有第一导电类型的半导体衬底，其具有第一区域和第二区域，每个具有第二导电类型，其间具有沟道区域。第一区域和第二区域沿第一方向排列。栅极电介质在沟道区域的至少一部分之上。栅极在栅极电介质上方，栅极在与第一区域，第二区域和沟道区域不重叠的终止点处沿横向于第一方向终止的方向延伸。铁电电容器处于终端点。铁电电容器具有第一端和第二端，第一端连接到栅极。铁电存储单元具有三个端子：第一区域，第二区域和第二端子。在另一个实施例中，绝缘体在第一区域的至少一部分之上。栅极的一端位于栅极电介质上，并在绝缘体上延伸，终止于终止点。铁电电容器连接到位于第一区域的一部分上的终止点。

39. 发明申请

US20050213386A1 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 有权
公开(公告)号：US20050213386A1
公开(公告)日：2005-09-29
申请号：US11078562
申请日：2005-02-28
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

40. 发明申请

US20050045940A1 SELF-ALIGNED METHOD OF FORMING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED FLOATING GATE, AND A MEMORY ARRAY MADE THEREBY 有权
标题翻译：形成具有浮动门的浮动存储器存储器的半导体存储器阵列的自对准方法及其存储器阵列
公开(公告)号：US20050045940A1
公开(公告)日：2005-03-03
申请号：US10653015
申请日：2003-08-28
申请人： Bomy Chen , Dana Lee , Hieu Tran
发明人： Bomy Chen , Dana Lee , Hieu Tran
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7885
摘要： An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.
摘要翻译：一种浮动栅极存储单元的阵列及其制造方法，其中每对存储单元包括形成在半导体衬底的表面中的一对沟槽，其中衬底的条带设置在其间，源区域形成在衬底条，一对漏极区，一对沟道区，每个沟道区各自在源极区和漏极区之一之间延伸;一对浮置栅极，分别设置在一个沟槽中，以及一对控制栅极。每个通道区域具有设置在衬底条中并沿其中一个沟槽延伸的第一部分，在一个沟槽下面延伸的第二部分，沿该沟槽延伸的第三部分，以及沿衬底表面延伸的第四部分的控制门。

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