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1. 发明授权

US07119396B2 NROM device 有权
标题翻译： NROM设备
公开(公告)号：US07119396B2
公开(公告)日：2006-10-10
申请号：US10962008
申请日：2004-10-08
申请人： Bomy Chen , Dana Lee , Yaw Wen Hu , Bing Yeh
发明人： Bomy Chen , Dana Lee , Yaw Wen Hu , Bing Yeh
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11568 , H01L29/66553
摘要： A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.
摘要翻译：一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸，电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

2. 发明授权

US06806531B1 Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation 有权
公开(公告)号：US06806531B1
公开(公告)日：2004-10-19
申请号：US10409248
申请日：2003-04-07
申请人： Bomy Chen , Dana Lee , Bing Yeh
发明人： Bomy Chen , Dana Lee , Bing Yeh
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/66825
摘要： A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.

3. 发明授权

US06913975B2 Non-volatile floating gate memory cell with floating gates formed in cavities, and array thereof, and method of formation 有权
标题翻译：具有形成在空腔中的浮动栅极的非易失性浮动栅极存储单元及其阵列，以及形成方法
公开(公告)号：US06913975B2
公开(公告)日：2005-07-05
申请号：US10885923
申请日：2004-07-06
申请人： Bomy Chen , Dana Lee , Bing Yeh
发明人： Bomy Chen , Dana Lee , Bing Yeh
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/66825
摘要： A non-volatile memory cell has a single crystalline semiconductive material, such as single crystalline silicon, of a first conductivity type. A first and a second region each of a second conductivity type, different from the first conductivity type, spaced apart from one another is formed in the semiconductive material. A channel region, having a first portion, and a second portion, connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A floating gate, which can be conductive or non-conductive, is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region, with the first floating gate having generally a triangular shape. The floating gate is formed in a cavity. A gate electrode is capacitively coupled to the first floating gate, and is spaced apart from the second portion of the channel region. The second portion of the channel region is between the first portion and the second region. A bi-directional non-volatile memory cell has two floating gates each formed in a cavity. A method of making the non-volatile memory cell and the array are also disclosed.
摘要翻译：非易失性存储单元具有第一导电类型的单结晶硅单晶硅。在半导体材料中形成有彼此间隔开的与第一导电类型不同的第二导电类型的第一和第二区域。具有第一部分的通道区域和第二部分连接用于电荷传导的第一和第二区域。电介质在沟道区上。可以是导电或非导电的浮动栅极位于电介质上，与沟道区的第一部分间隔开。沟道区域的第一部分与第一区域相邻，第一浮栅具有大致三角形形状。浮动门形成在空腔中。栅极电极电容耦合到第一浮动栅极，并且与沟道区域的第二部分间隔开。沟道区域的第二部分在第一部分和第二区域之间。双向非易失性存储单元具有分别形成在空腔中的两个浮动栅极。还公开了制造非易失性存储单元和阵列的方法。

4. 发明申请

US20060079053A1 NROM device and method of making same 有权
标题翻译： NROM设备及其制作方法
公开(公告)号：US20060079053A1
公开(公告)日：2006-04-13
申请号：US10962008
申请日：2004-10-08
申请人： Bomy Chen , Dana Lee , Yaw Hu , Bing Yeh
发明人： Bomy Chen , Dana Lee , Yaw Hu , Bing Yeh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11568 , H01L29/66553
摘要： A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.
摘要翻译：一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸，电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

5. 发明授权

US06822287B1 Array of integrated circuit units with strapping lines to prevent punch through 有权
标题翻译：具有捆扎线的集成电路单元阵列，以防止穿透
公开(公告)号：US06822287B1
公开(公告)日：2004-11-23
申请号：US10452027
申请日：2003-05-30
申请人： Dana Lee , Yaw Wen Hu
发明人： Dana Lee , Yaw Wen Hu
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , G11C5/063 , G11C16/0425 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11553 , H01L27/11556 , H01L29/42336 , H01L29/7885
摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. A first plurality of row lines electrically connect the second region of cells in the same row. A plurality of column lines electrically connect the first region of cells in the same column. A plurality of strap lines connect certain of the row lines with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another, wherein row lines connected to a first strap line are interleaved with row lines connected to a second strap line.
摘要翻译：非易失性存储单元的阵列被布置在多个行和列中，其中每个单元具有第一区域和彼此间隔开的第二区域，其间具有沟道区域，用于在第一区域和第二区域之间传导电荷地区。第一组多条行线电连接同一行中的第二区域的单元。多个列线电连接同一列中的第一区域的单元。多条绑带线连接某些行线，每条绑带线电连接彼此不紧邻的第二多条行线，其中连接到第一绑带线的行线与连接到第二绑带线的行线交错。

6. 发明授权

US07180127B2 Semiconductor memory array of floating gate memory cells with buried floating gate, pointed floating gate and pointed channel region 有权
标题翻译：半导体存储器阵列的浮动栅极存储单元具有埋入浮栅，尖浮栅和尖通道区
公开(公告)号：US07180127B2
公开(公告)日：2007-02-20
申请号：US10872052
申请日：2004-06-17
申请人： Bomy Chen , Dana Lee
发明人： Bomy Chen , Dana Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7885
摘要： A method of forming a floating gate memory cell array, and the array formed thereby, wherein a trench is formed into the surface of a semiconductor substrate. The source and drain regions are formed underneath the trench and along the substrate surface, respectively, with a non-linear channel region therebetween. The floating gate has a lower portion disposed in the trench and an upper portion disposed above the substrate surface and having a lateral protrusion extending parallel to the substrate surface. The lateral protrusion is formed by etching a cavity into an exposed end of a sacrificial layer and filling it with polysilicon. The control gate is formed about the lateral protrusion and is insulated therefrom. The trench sidewall meets the substrate surface at an acute angle to form a sharp edge that points toward the floating gate and in a direction opposite to that of the lateral protrusion.
摘要翻译：一种形成浮栅存储单元阵列的方法和由此形成的阵列，其中沟槽形成在半导体衬底的表面中。源极和漏极区分别形成在沟槽下方并且沿着衬底表面，其间具有非线性沟道区。浮动栅极具有设置在沟槽中的下部和设置在基板表面上方并具有平行于基板表面延伸的横向突起的上部。横向突起通过将空腔蚀刻到牺牲层的暴露端并用多晶硅填充而形成。控制门围绕横向突起形成并与其绝缘。沟槽侧壁以锐角与衬底表面相接触以形成指向浮动栅极并且沿与横向突起的方向相反的方向的尖锐边缘。

7. 发明授权

US06992909B2 Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array 有权
标题翻译：用于存储n> 4个可能状态之一并且具有双向读取的多位ROM单元，这种单元的阵列，以及用于制作阵列的方法
公开(公告)号：US06992909B2
公开(公告)日：2006-01-31
申请号：US11157318
申请日：2005-06-20
申请人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
发明人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
IPC分类号： G11C17/00
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/12 , H01L27/1126 , H01L27/11266
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。门间隔开并与通道的至少第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

8. 发明申请

US20050104116A1 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US20050104116A1
公开(公告)日：2005-05-19
申请号：US10714243
申请日：2003-11-13
申请人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

9. 发明授权

US07358559B2 Bi-directional read/program non-volatile floating gate memory array, and method of formation 有权
标题翻译：双向读/写非挥发性浮栅存储器阵列及其形成方法
公开(公告)号：US07358559B2
公开(公告)日：2008-04-15
申请号：US11239791
申请日：2005-09-29
申请人： Felix (Ying-Kit) Tsui , Jeng-Wei Yang , Bomy Chen , Chun-Ming Chen , Dana Lee , Changyuan Chen
发明人： Felix (Ying-Kit) Tsui , Jeng-Wei Yang , Bomy Chen , Chun-Ming Chen , Dana Lee , Changyuan Chen
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336
摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.
摘要翻译：双向读/写非易失性存储单元和阵列能够实现高密度。每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。控制栅极连接到每个源极/漏极区域，并且还电容耦合到浮动栅极。通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。双向读取允许将单元编程为存储位，每个浮动栅极中有一位。这种存储单元的阵列包括彼此相邻的活性区域中的细胞排，所述活性区域通过没有任何隔离材料的半导体衬底材料彼此分开。相同列中的单元具有共同的源极/漏极区域，共同的漏极/源极区域以及每个沟槽中的第一和第二控制栅极共同。相邻列中的单元具有共同的源极/漏极，第一个控制栅极共同。

10. 发明授权

US06927993B2 Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells 有权
标题翻译：用于存储N> 4个可能状态并具有双向读取的多位ROM单元，这样的单元阵列
公开(公告)号：US06927993B2
公开(公告)日：2005-08-09
申请号：US10642079
申请日：2003-08-14
申请人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
发明人： Bomy Chen , Kai Man Yue , Dana Lee , Feng Gao
IPC分类号： G11C11/56 , G11C17/00 , G11C17/12 , H01L21/8236 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/112 , G11C11/5692 , G11C17/12 , H01L27/1126 , H01L27/11266
摘要： A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together. ROM cells in the same column have the first regions connected in a common first column, and second regions connected in common second column. Finally, ROM cells in adjacent columns to one side share a common first column, and cells in adjacent columns to another side share a common second column.
摘要翻译：多位只读存储器（ROM）单元的阵列位于具有第一浓度的第一导电类型的半导体衬底中。每个ROM单元具有在基板中彼此间隔开的第二导电类型的第一和第二区域。通道在第一和第二区域之间。通道具有三个部分，第一部分，第二部分和第三部分。栅极间隔开并且至少与通道的第二部分绝缘。每个ROM单元具有多个N个可能状态中的一个，其中N大于2.每个ROM单元的状态由存在或不存在在通道的第一部分中形成并与通道的第一部分相邻第一区域和/或与第二区域相邻的通道的第三部分。在集成电路器件的其他部分的MOS晶体管中形成扩展或光晕的同时形成这些扩展和光晕，从而降低成本。 ROM单元的阵列被布置成多个行和列，其中同一行中的ROM单元的门连接在一起。同一列中的ROM单元具有连接在公共第一列中的第一区域和连接在公共第二列中的第二区域。最后，一侧的相邻列中的ROM单元共享一个共同的第一列，另一侧的相邻列中的单元格共享第二列。

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