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31. 发明申请

US20080237700A1 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US20080237700A1
公开(公告)日：2008-10-02
申请号：US12078143
申请日：2008-03-27
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

32. 发明申请

US20070257302A1 Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件及其形成方法
公开(公告)号：US20070257302A1
公开(公告)日：2007-11-08
申请号：US11797401
申请日：2007-05-03
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的插塞使多晶硅层通过开口接触。

33. 发明授权

US07256631B2 Charge pump with balanced and constant up and down currents 有权
标题翻译：电荷泵具有平衡和恒定的上下电流
公开(公告)号：US07256631B2
公开(公告)日：2007-08-14
申请号：US11188833
申请日：2005-07-25
申请人： Ju-Hyung Kim
发明人： Ju-Hyung Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0895
摘要： A charge pump generates a first sub up current and a second sub up current that vary complementarily with a change in a voltage at an output terminal. The charge pump also generates a first sub down current and a second sub down current that vary complementarily with the change in the voltage at the output terminal. With such complementary relationships, the total up/down currents remain substantially constant and balanced with the change in the voltage at the output terminal.
摘要翻译：电荷泵产生与输出端子处的电压变化互补地变化的第一次上升电流和第二次上升电流。电荷泵还产生与输出端子处的电压变化互补地变化的第一次降压电流和第二次降压电流。通过这种互补关系，总上升/下降电流保持基本恒定，并与输出端子电压的变化相平衡。

34. 发明授权

US09559080B2 Integrated circuit device packages and methods for manufacturing integrated circuit device packages 有权
标题翻译：集成电路器件封装以及用于制造集成电路器件封装的方法
公开(公告)号：US09559080B2
公开(公告)日：2017-01-31
申请号：US14395116
申请日：2013-03-18
申请人： Jae-Sung Lim , Ju-Hyung Kim , Jin-Wook Jeong , Hyun-Joo Kim , Hyouk Lee
发明人： Jae-Sung Lim , Ju-Hyung Kim , Jin-Wook Jeong , Hyun-Joo Kim , Hyouk Lee
IPC分类号： H01L21/02 , H01L25/065 , H01L23/498 , H01L23/538 , H01L23/00 , H01L21/768 , H01L23/04 , H01L23/522 , H01L23/528 , H01L23/532 , H01L25/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/768 , H01L23/04 , H01L23/3121 , H01L23/3135 , H01L23/4985 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5389 , H01L23/564 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/04105 , H01L2224/16145 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/73209 , H01L2224/73267 , H01L2224/8203 , H01L2224/821 , H01L2224/9202 , H01L2224/92144 , H01L2224/92244 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/12042 , H01L2924/00
摘要： An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.
摘要翻译：集成电路器件封装可以包括具有第一布线的柔性基板，具有第二布线的集成电路器件，具有第一开口的柔性绝缘结构和分别暴露第一布线和第二布线的第二开口;第三布线将第一布线电连接到第二布线，以及覆盖第三布线的柔性保护构件。层叠的柔性集成电路器件封装可以包括柔性衬底，包括第一连接焊盘的第一柔性集成电路器件，包括第二连接焊盘的第二柔性集成电路器件，将第一和第二连接焊盘电连接到外部装置和设置在第二柔性集成电路装置上的柔性保护构件。

35. 发明授权

US09299970B2 Jelly-roll type battery unit and winding method thereof and lithium secondary battery comprising the same 有权
标题翻译：胶卷式电池单元及其卷绕方法以及包含该方法的锂二次电池
公开(公告)号：US09299970B2
公开(公告)日：2016-03-29
申请号：US10748197
申请日：2003-12-31
申请人： Chang-Seob Kim , Ju-Hyung Kim , Min-Ho Song , Jung-Won Kang
发明人： Chang-Seob Kim , Ju-Hyung Kim , Min-Ho Song , Jung-Won Kang
IPC分类号： H01M4/70 , H01M2/26 , H01M10/052 , H01M10/0587
CPC分类号： H01M2/263 , H01M4/70 , H01M10/052 , H01M10/0587 , Y02E60/122 , Y10T29/49108 , Y10T29/49114
摘要： A jelly-roll type battery unit, a winding method thereof and a lithium secondary battery comprising the battery unit include a first electrode plate having a first electrode current collector with a first electrode tab and a first electrode active material layer coated on at least one surface of the first electrode current collector, a second electrode plate having a second electrode current collector with a second electrode tab and a second electrode active material layer coated on at least one surface of the second electrode current collector, and a separator that is interposed between the first electrode plate and the second electrode plate, wherein the electrode tab is incorporated into the electrode current collector in an area of either the first or the second electrode plate where the corresponding electrode active material layer is not coated. Since an electrode tab is formed by cutting a portion of an electrode current collector and folding upward, deformation of a jelly-roll type battery unit is prevented.
摘要翻译：果冻卷型电池单元，其卷绕方法和包括该电池单元的锂二次电池包括具有第一电极集电器的第一电极板，第一电极集电器具有第一电极接线片和涂覆在至少一个表面上的第一电极活性材料层的第二电极集电体，具有第二电极集电体的第二电极集电体，其具有第二电极接线片和涂覆在第二电极集电体的至少一个表面上的第二电极活性材料层，以及隔板，第一电极板和第二电极板，其中，电极接线片在没有涂覆相应的电极活性物质层的第一或第二电极板的区域中结合到电极集电器中。由于通过切割电极集电体的一部分并向上折叠来形成电极片，因此防止了胶卷型电池单元的变形。

36. 发明申请

US20150076683A1 Integrated Circuit Device Packages And Methods for Manufacturing Integrated Circuit Device Packages 有权
标题翻译：集成电路器件封装及制造集成电路器件封装的方法
公开(公告)号：US20150076683A1
公开(公告)日：2015-03-19
申请号：US14395116
申请日：2013-03-18
申请人： Jae-Sung Lim , Ju-Hyung Kim , Jin-Wook Jeong , Hyun-Joo Kim , Hyouk Lee
发明人： Jae-Sung Lim , Ju-Hyung Kim , Jin-Wook Jeong , Hyun-Joo Kim , Hyouk Lee
IPC分类号： H01L25/065 , H01L23/528 , H01L21/768 , H01L23/522 , H01L25/00 , H01L23/04 , H01L23/00 , H01L23/532
CPC分类号： H01L25/0657 , H01L21/768 , H01L23/04 , H01L23/3121 , H01L23/3135 , H01L23/4985 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5389 , H01L23/564 , H01L24/16 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/50 , H01L2224/04105 , H01L2224/16145 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/73209 , H01L2224/73267 , H01L2224/8203 , H01L2224/821 , H01L2224/9202 , H01L2224/92144 , H01L2224/92244 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/12042 , H01L2924/00
摘要： An integrated circuit device package may include a flexible substrate having a first wiring, an integrated circuit device having a second wiring, a flexible insulation structure having a first opening and a second opening exposing the first wiring and the second wiring, respectively, a third wiring electrically connecting the first wiring to the second wiring, and a flexible protection member covering the third wiring. A stacked flexible integrated circuit device package may include a flexible substrate, a first flexible integrated circuit device including a first connection pad, a second flexible integrated circuit device including a second connection pad, a connection wiring electrically connecting the first and the second connection pads to an external device, and a flexible protection member disposed on the second flexible integrated circuit device.
摘要翻译：集成电路器件封装可以包括具有第一布线的柔性基板，具有第二布线的集成电路器件，具有第一开口的柔性绝缘结构和分别暴露第一布线和第二布线的第二开口;第三布线将第一布线电连接到第二布线，以及覆盖第三布线的柔性保护构件。层叠的柔性集成电路器件封装可以包括柔性衬底，包括第一连接焊盘的第一柔性集成电路器件，包括第二连接焊盘的第二柔性集成电路器件，将第一和第二连接焊盘电连接到外部装置和设置在第二柔性集成电路装置上的柔性保护构件。

37. 发明授权

US08546870B2 Semiconductor devices having gate structures with conductive patterns of different widths and methods of fabricating such devices 有权
标题翻译：具有具有不同宽度的导电图案的栅极结构的半导体器件和制造这种器件的方法
公开(公告)号：US08546870B2
公开(公告)日：2013-10-01
申请号：US12622594
申请日：2009-11-20
申请人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
发明人： Ju-Hyung Kim , Chang-Seok Kang , Sung-Il Chang , Young-Woo Park , Jung-Dal Choi
IPC分类号： H01L29/792
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L29/4234
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括依次层叠在半导体衬底上的第一电介质图案，数据存储图案和第二电介质图案。在第二电介质图案上提供第一导电图案。具有比第一导电图案更大的宽度的第二导电图案设置在第一导电图案上。

38. 发明授权

US07999307B2 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US07999307B2
公开(公告)日：2011-08-16
申请号：US12923998
申请日：2010-10-20
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

39. 发明申请

US20100301425A1 SEMICONDUCTOR DEVICE HAVING A GATE CONTACT STRUCTURE CAPABLE OF REDUCING INTERFACIAL RESISTANCE 有权
标题翻译：具有能够降低界面电阻的门接触结构的半导体器件
公开(公告)号：US20100301425A1
公开(公告)日：2010-12-02
申请号：US12856295
申请日：2010-08-13
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞使多晶硅层通过开口接触。

40. 发明授权

US07842997B2 Nonvolatile memory device having cell and peripheral regions and method of making the same 有权
标题翻译：具有单元和外围区域的非易失性存储器件及其制造方法
公开(公告)号：US07842997B2
公开(公告)日：2010-11-30
申请号：US12078143
申请日：2008-03-27
申请人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
发明人： Ju-Hyung Kim , Jung-Dal Choi , Jang-Hyun You
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A nonvolatile memory device and method of making the same are provided. Memory cells may be provided in a cell area wherein each memory cell has an insulative structure including a tunnel insulating layer, a floating trap layer and a blocking layer, and a conductive structure including an energy barrier layer, a barrier metal layer and a low resistance gate electrode. A material having a lower resistivity may be used as the gate electrode so as to avoid problems associated with increased resistance and to allow the gate electrode to be made relatively thin. The memory device may further include transistors in the peripheral area, which may have a gate dielectric layer, a lower gate electrode of poly-silicon and an upper gate electrode made of metal silicide, allowing an improved interface with the lower gate electrode without diffusion or reaction while providing a lower resistance.
摘要翻译：提供了一种非易失性存储器件及其制造方法。存储单元可以设置在单元区域中，其中每个存储单元具有包括隧道绝缘层，浮动陷阱层和阻挡层的绝缘结构，以及包括能量阻挡层，阻挡金属层和低电阻的导电结构栅电极。可以使用具有较低电阻率的材料作为栅电极，以避免与电阻增加相关的问题，并允许栅电极相对较薄。存储器件还可以包括在外围区域中的晶体管，其可以具有栅极电介质层，多晶硅的下部栅电极和由金属硅化物制成的上部栅电极，从而允许与下部栅电极的改善的界面而不扩散或同时提供较低的电阻。

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