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31. 发明授权

US07009895B2 Method for skip over redundancy decode with very low overhead 有权
标题翻译：用于以非常低的开销跳过冗余解码的方法
公开(公告)号：US07009895B2
公开(公告)日：2006-03-07
申请号：US10814719
申请日：2004-03-31
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/848
摘要： The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track. This reduces the number of wire tracks from 1 track per I/O to 1 track per 2 I/Os.
摘要翻译：所描述的方法使用跳过技术，其需要在待修复的块的输入和输出处的一组复用器。实现I / O冗余控制逻辑的改进方法对芯片面积和芯片线轨都具有最小的影响。为了克服在不期望的芯片上所需的房地产使用的问题，可以使用可以共享单个线路的奇数和偶数解码器输出，同样的线可用于奇数和偶数解码器输出。为了实现作为集中功能的解码和携带功能，出现了逻辑上相邻的解码电路（通过进位信号连接的解码器）应物理上靠近在一起以最小化进位线路开销的要求。如果解码结构和多路复用结构彼此正交配置，则每个解码器输出将需要线轨。然而，所描述的方法允许奇数和偶数解码器输出共享相同的线轨道。这减少了每个I / O从1个磁道到每2个I / O到1个磁道的电线轨迹数量。

32. 发明授权

US06584023B1 System for implementing a column redundancy scheme for arrays with controls that span multiple data bits 失效
标题翻译：用于实现具有跨多个数据位的控件的数组的列冗余方案的系统
公开(公告)号：US06584023B1
公开(公告)日：2003-06-24
申请号：US10043024
申请日：2002-01-09
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/848
摘要： An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data bits for receiving data inputs, a spare data bit and a field control input line. Also included in the system is circuitry to separate a field control signal from the field control input line into one or more individual control signals for activating a corresponding data bit in the array or for input to a multiplexor. The system further comprises circuitry to steer around a defective data bit in the array. This circuitry includes: a field control signal multiplexor corresponding to each field control signal; a spare control signal multiplexor to activate the spare data bit; a data multiplexor corresponding to each of the data bits in the array; and a spare data multiplexor to steer one of the data inputs to the spare data bit. The system also includes programmable logic in communication with the field control signal multiplexor, the spare control signal multiplexor, the data multiplexor and the spare data multiplexor to cause the steer around to take place in response to detecting a defective data bit in the array.
摘要翻译：本发明的示例性实施例是用于对具有跨越多个数据位的控制的阵列实现列冗余方案的系统。该系统包括用于接收数据输入的数据位阵列，备用数据位和场控制输入线。还包括在系统中的电路是将场控制信号与场控制输入线分离成一个或多个单独的控制信号，用于激活阵列中相应的数据位或输入到多路复用器。该系统还包括用于控制阵列中的有缺陷的数据位的电路。该电路包括：对应于每个场控制信号的场控制信号多路复用器; 备用控制信号多路复用器，用于激活备用数据位; 与阵列中的每个数据位相对应的数据多路复用器; 以及备用数据多路复用器，以将数据输入中的一个引导到备用数据位。该系统还包括与现场控制信号多路复用器，备用控制信号多路复用器，数据多路复用器和备用数据多路复用器通信的可编程逻辑，以响应于检测到阵列中的有缺陷的数据位而引起转向。

33. 发明授权

US08937840B2 Digital voltage boost circuit 有权
标题翻译：数字升压电路
公开(公告)号：US08937840B2
公开(公告)日：2015-01-20
申请号：US13326727
申请日：2011-12-15
申请人： James W. Dawson , Noam Jungmann , Elazar Kachir , Udi Nir , Donald W. Plass
发明人： James W. Dawson , Noam Jungmann , Elazar Kachir , Udi Nir , Donald W. Plass
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle.
摘要翻译：可选地与模拟电压调节器并联的数字升压电路周期性地将恒定量的电流每周期注入高密度存储器阵列的位线，以消除否则将发生的偏置电压降低。这导致恢复时间快得多，并减少了所需的半导体房地产。升压电路中的脉冲发生器产生一个或多个电流调制信号，其控制电流源中的相应的电流供应装置。升压电路驱动每个存储周期对偏置电压节点的恒定电流量。

34. 发明授权

US08605528B2 Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods 失效
标题翻译：具有隔离预充电架构的感测放大器，结合了这种读出放大器的存储电路和相关联的方法
公开(公告)号：US08605528B2
公开(公告)日：2013-12-10
申请号：US13288424
申请日：2011-11-03
申请人： John E. Barth, Jr. , Donald W. Plass , Adis Vehabovic
发明人： John E. Barth, Jr. , Donald W. Plass , Adis Vehabovic
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C11/4091
摘要： Disclosed are a sense amplifier and a memory circuit that incorporates it. The amplifier comprises cross-coupled inverters, each with a pull-down transistor and a pull-up transistor connected in series. One inverter has a voltage-controlled switch controlling the electrical connection between drain nodes of the transistors. During a read operation, the pull-up transistor drain node is pre-charged high and the pull-down transistor drain node receives an input signal. The switch is tripped, thereby making the electrical connection only when the voltage at the pull-down transistor drain node is less than the switch's trip voltage. In this case, the sense node discharges to the same level as the input signal. Otherwise, the switch prevents the electrical connection and the sense node remains high. The trip voltage depends on a reference voltage, which can be variable, thereby allowing the sensitivity of the sense amplifier to be selectively adjusted. Also disclosed are associated methods.
摘要翻译：公开了一种读出放大器和包含它的存储器电路。放大器包括交叉耦合的反相器，每个具有串联的下拉晶体管和上拉晶体管。一个逆变器具有控制晶体管的漏极节点之间的电连接的电压控制开关。在读操作期间，上拉晶体管漏极节点被预充电为高电平，并且下拉晶体管漏极节点接收输入信号。开关跳闸，从而仅在下拉式晶体管漏极节点处的电压小于开关跳闸电压时进行电气连接。在这种情况下，感测节点放电到与输入信号相同的电平。否则，交换机可防止电气连接，并且感测节点保持高电平。跳闸电压取决于可以变化的参考电压，从而允许选择性地调节读出放大器的灵敏度。还公开了相关联的方法。

35. 发明授权

US08214592B2 Dynamic runtime modification of array layout for offset 有权
标题翻译：用于偏移的数组布局的动态运行时修改
公开(公告)号：US08214592B2
公开(公告)日：2012-07-03
申请号：US12424348
申请日：2009-04-15
申请人： Ravi K. Arimilli , Donald W. Plass , William John Starke
发明人： Ravi K. Arimilli , Donald W. Plass , William John Starke
IPC分类号： G06F13/16
CPC分类号： G06F12/0886 , G06F9/30047 , G06F9/345
摘要： Disclosed are a method, a system and a computer program product for operating a cache system. The cache system can include multiple cache lines, and a first cache line of the multiple of cache lines can include multiple cache cells, and a bus coupled to the multiple cache cells. In one or more embodiments, the bus can include a switch that is operable to receive a first control signal and to split the bus into first and second portions or aggregate the bus into a whole based on the first control signal. When the bus is split, a first cache cell and a second cache cell of the multiple cache cells are coupled to respective first and second portions of the bus. Data from the first and second cache cells can be selected through respective portions of the bus and outputted through a port of the cache system.
摘要翻译：公开了一种用于操作缓存系统的方法，系统和计算机程序产品。高速缓存系统可以包括多个高速缓存行，并且多条高速缓存行的第一高速缓存行可以包括多个高速缓存单元，以及耦合到多个高速缓存单元的总线。在一个或多个实施例中，总线可以包括可操作以接收第一控制信号并且将总线分为第一和第二部分或基于第一控制信号将总线聚合成整体的开关。当总线被分离时，多个高速缓存单元的第一高速缓存单元和第二高速缓存单元耦合到总线的相应的第一和第二部分。可以通过总线的各个部分选择来自第一和第二高速缓存单元的数据，并通过高速缓存系统的端口输出。

36. 发明申请

US20090034345A1 Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line 失效
标题翻译：八个晶体管SRAM单元，只需要一个字线即可提高稳定性
公开(公告)号：US20090034345A1
公开(公告)日：2009-02-05
申请号：US11832190
申请日：2007-08-01
申请人： Yuen H. Chan , William V. Huott , Donald W. Plass
发明人： Yuen H. Chan , William V. Huott , Donald W. Plass
IPC分类号： G11C7/00
CPC分类号： G11C11/412 , G11C8/14
摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.
摘要翻译：由单个字线访问的SRAM单元和用于读取和写入操作的单独的存取晶体管。一对写位线传输器件分别提供用于写操作的交叉耦合上拉，下拉晶体管对的右侧和左侧的访问以及与字线晶体管串联的单个读取位线晶体管，当选中，读取单元格的内容。

37. 发明授权

US07437626B2 Efficient method of test and soft repair of SRAM with redundancy 有权
标题翻译： SRAM冗余测试和软修复的高效方法
公开(公告)号：US07437626B2
公开(公告)日：2008-10-14
申请号：US11056726
申请日：2005-02-11
申请人： Tom Y. Chang , William V. Huott , Thomas J. Knips , Donald W. Plass
发明人： Tom Y. Chang , William V. Huott , Thomas J. Knips , Donald W. Plass
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译：使用包括简单数据历史表在内的自检内置阵列。该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。

38. 发明授权

US07295457B2 Integrated circuit chip with improved array stability 失效
标题翻译：集成电路芯片具有改进的阵列稳定性
公开(公告)号：US07295457B2
公开(公告)日：2007-11-13
申请号：US10950940
申请日：2004-09-27
申请人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
发明人： Yuen H. Chan , Rajiv V. Joshi , Donald W. Plass
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译：可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。正常基极FET具有基极阈值，并且定制的FET具有高于阈值。在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

39. 发明授权

US07099206B2 High density bitline selection apparatus for semiconductor memory devices 失效
公开(公告)号：US07099206B2
公开(公告)日：2006-08-29
申请号：US11046101
申请日：2005-01-28
申请人： James W. Dawson , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C7/12 , G11C7/18 , G11C8/10 , G11C2207/002
摘要： A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

40. 发明授权

US07085173B1 Write driver circuit for memory array 失效
标题翻译：为存储器阵列写入驱动电路
公开(公告)号：US07085173B1
公开(公告)日：2006-08-01
申请号：US11054270
申请日：2005-02-09
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1078 , G11C7/1096
摘要： Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global bitline. A clamping device is coupled to the interface line, the clamping device coupling the interface line to ground in response to a data in signal. A memory having the circuit is also disclosed.
摘要翻译：本发明的实施例包括用于将本地位线与全局位线接口的电路。该电路包括通过本地位线装置耦合到本地位线的接口线。全局输出设备具有耦合到接口线的输入和耦合到全局位线的输出。夹紧装置耦合到接口线，夹紧装置响应于信号中的数据将接口线耦合到地。还公开了一种具有该电路的存储器。

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