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31. 发明申请

US20100091562A1 TEMPERATURE DEPENDENT SYSTEM FOR READING ST-RAM 失效
标题翻译：用于读取ST-RAM的温度依赖系统
公开(公告)号：US20100091562A1
公开(公告)日：2010-04-15
申请号：US12250036
申请日：2008-10-13
申请人： Yiran Chen , Hai Li , Hongyue Liu , Henry F. Huang , Yong Lu
发明人： Yiran Chen , Hai Li , Hongyue Liu , Henry F. Huang , Yong Lu
IPC分类号： G11C7/00 , G11C11/02
CPC分类号： G11C7/04 , G11C11/1659 , G11C11/1673
摘要： A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell.
摘要翻译：一种包括至少一个存储单元的存储器件，所述存储单元包括：磁性隧道结（MTJ）; 和晶体管，其中所述晶体管可操作地耦合到所述MTJ; 有点线源线; 和字线，其中所述存储器单元可操作地耦合在所述位线和所述源极线之间，并且所述字线可操作地耦合到所述晶体管; 温度传感器; 以及控制电路，其中所述温度传感器可操作地耦合到所述控制电路，并且所述控制电路和温度传感器被配置为控制横跨所述存储器单元的电流。

32. 发明申请

US20130003448A1 MRAM DIODE ARRAY AND ACCESS METHOD 有权
标题翻译： MRAM二极管阵列和访问方法
公开(公告)号：US20130003448A1
公开(公告)日：2013-01-03
申请号：US13611225
申请日：2012-09-12
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

33. 发明授权

US08289746B2 MRAM diode array and access method 有权
标题翻译： MRAM二极管阵列和访问方式
公开(公告)号：US08289746B2
公开(公告)日：2012-10-16
申请号：US12948824
申请日：2010-11-18
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Song S. Xue
IPC分类号： G11C5/08 , G11C27/00 , G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.
摘要翻译：存储单元包括磁性隧道结数据单元电耦合到位线和源极线。磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

34. 发明授权

US07936629B2 Table-based reference voltage characterization scheme 有权
标题翻译：基于表的参考电压表征方案
公开(公告)号：US07936629B2
公开(公告)日：2011-05-03
申请号：US12352722
申请日：2009-01-13
申请人： Henry F. Huang , Andrew J. Carter , Maroun Khoury , Yong Lu , Yiran Chen
发明人： Henry F. Huang , Andrew J. Carter , Maroun Khoury , Yong Lu , Yiran Chen
IPC分类号： G11C7/02
CPC分类号： G11C5/147 , G11C11/1673 , G11C13/0069
摘要： Method and apparatus for reading data from a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, at least a first and second memory cell are read for a plurality of resistance values that are used to select and store a voltage reference for each memory cell.
摘要翻译：用于从诸如修改的STRAM单元的非易失性存储单元读取数据的方法和装置。在一些实施例中，针对用于选择和存储每个存储器单元的电压参考的多个电阻值，读取至少第一和第二存储单元。

35. 发明申请

US20110029714A1 RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY 有权
标题翻译：具有部分块更新能力的电阻式感知存储器阵列
公开(公告)号：US20110029714A1
公开(公告)日：2011-02-03
申请号：US12904653
申请日：2010-10-14
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li
IPC分类号： G06F12/00 , G11C11/21 , G11C11/16
CPC分类号： G11C8/12 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/79
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
摘要翻译：本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。第一组用户数据在第一PBA被写入所选择的块。通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

36. 发明申请

US20100177551A1 BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY 有权
标题翻译：用于电阻式感应存储器单元阵列的位设置模式
公开(公告)号：US20100177551A1
公开(公告)日：2010-07-15
申请号：US12352693
申请日：2009-01-13
申请人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
发明人： Yiran Chen , Daniel S. Reed , Yong Lu , Harry Hongyue Liu , Hai Li , Rod V. Bowman
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C11/16 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5685 , G11C13/0007 , G11C13/0026 , G11C13/0069
摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
摘要翻译：本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM））数组。根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

37. 发明申请

US20100118602A1 DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF 审中-公开
标题翻译：基于线路的双重存储器阵列和存储器单元
公开(公告)号：US20100118602A1
公开(公告)日：2010-05-13
申请号：US12270056
申请日：2008-11-13
申请人： Andrew John Carter , Yiran Chen , Yong Lu , Harry Hongyue Liu
发明人： Andrew John Carter , Yiran Chen , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/14
CPC分类号： G11C5/063 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C2213/72 , G11C2213/74
摘要： A memory array includes a plurality of first and second source, lines overlapping a plurality of bit lines, and a plurality of magnetic storage elements, each coupled to a corresponding first and second source line and to a corresponding bit line. Current may be driven, in first and second directions, through each magnetic element, for example, to program the elements. Diodes may be incorporated to avert sneak paths in the memory array. A first diode may be coupled between each magnetic element and the corresponding first source line, the first diode being biased to allow read and write current flow through the magnetic element, from the corresponding first source line; and a second diode may be coupled between each magnetic element and the corresponding second source line, the second diode being reverse-biased to block read and write current flow through the magnetic element, from the corresponding second source line.
摘要翻译：存储器阵列包括多个第一和第二源，与多个位线重叠的线，以及多个磁存储元件，每个磁存储元件分别耦合到对应的第一和第二源极线以及相应的位线。电流可以在第一和第二方向上通过每个磁性元件被驱动，例如编程元件。可以并入二极管以避免存储器阵列中的潜行路径。第一二极管可以耦合在每个磁性元件和对应的第一源极线之间，第一二极管被偏置以允许读取和写入电流从相应的第一源极线流过磁性元件; 并且第二二极管可以耦合在每个磁性元件和对应的第二源极线之间，所述第二二极管被反向偏置以阻挡从对应的第二源极线读取和写入通过磁性元件的电流。

38. 发明授权

US08199563B2 Transmission gate-based spin-transfer torque memory unit 有权
标题翻译：基于传输栅极的自旋转移转矩存储单元
公开(公告)号：US08199563B2
公开(公告)日：2012-06-12
申请号：US13149136
申请日：2011-05-31
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1675 , Y10S977/935
摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
摘要翻译：描述基于传输门的自旋转移转矩存储单元。存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

39. 发明申请

US20110228598A1 TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT 有权
标题翻译：基于传输门控的转子转矩记忆单元
公开(公告)号：US20110228598A1
公开(公告)日：2011-09-22
申请号：US13149136
申请日：2011-05-31
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
IPC分类号： G11C11/14
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1675 , Y10S977/935
摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
摘要翻译：描述基于传输门的自旋转移转矩存储单元。存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

40. 发明授权

US07974119B2 Transmission gate-based spin-transfer torque memory unit 有权
标题翻译：基于传输栅极的自旋转移转矩存储单元
公开(公告)号：US07974119B2
公开(公告)日：2011-07-05
申请号：US12170549
申请日：2008-07-10
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1675 , Y10S977/935
摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
摘要翻译：描述基于传输门的自旋转移转矩存储单元。存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

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