专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US6110782A Method to combine high voltage device and salicide process 有权
标题翻译：高压装置与自动化处理相结合的方法
公开(公告)号：US6110782A
公开(公告)日：2000-08-29
申请号：US195651
申请日：1998-11-19
申请人： Wen-Ting Chu , Chuan-Li Chang , Ming-Chon Ho , Chang-Song Lin , Di-Son Kwo
发明人： Wen-Ting Chu , Chuan-Li Chang , Ming-Chon Ho , Chang-Song Lin , Di-Son Kwo
IPC分类号： H01L21/8234 , H01L21/8247
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/11541
摘要： A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low voltage device area from a high voltage device area. A gate oxide layer is grown in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. A first photomask is formed over a portion of the high voltage device area wherein the first photomask also completely covers the low voltage device area. The polysilicon layer is etched away where it is not covered by the photomask to form a high voltage device. Ions are implanted to form lightly doped source and drain regions within the semiconductor substrate adjacent to the high voltage device wherein the first photomask protects the polysilicon layer in the low voltage device area from the ions. The first photomask is removed. A second photomask is formed over a portion of the low voltage device area where a gate electrode is to be formed wherein the second photomask also completely covers the high voltage device area. The polysilicon layer not covered by the second photomask is etched away to form the gate electrode. The second photomask is removed. The low voltage and high voltage area devices are silicided and the fabrication of the integrated circuit device is completed.
摘要翻译：描述了在单个晶片上制造高电压和低压器件中的自对准硅化物和高电压器件工艺的集成方法。在半导体衬底上形成隔离区域，该半导体衬底围绕低电压器件区域和高电压器件区域电隔离。在器件区域中生长栅极氧化物层。沉积覆盖栅极氧化物层和隔离区的多晶硅层。第一光掩模形成在高电压器件区域的一部分上，其中第一光掩模也完全覆盖低电压器件区域。多晶硅层被蚀刻掉，其未被光掩模覆盖以形成高压器件。植入离子以在与高压器件相邻的半导体衬底内形成轻掺杂的源极和漏极区，其中第一光掩模保护低电压器件区域中的多晶硅层与离子。第一个光掩模被删除。第二光掩模形成在要形成栅电极的低电压器件区域的一部分上，其中第二光掩模也完全覆盖高电压器件区域。蚀刻掉未被第二光掩模覆盖的多晶硅层以形成栅电极。第二个光掩模被删除。低电压和高电压区域的器件被硅化，并且完成了集成电路器件的制造。

32. 发明授权

US06787418B2 Method of making the selection gate in a split-gate flash eeprom cell and its structure 失效
标题翻译：在分闸式闪光电池中制作选择栅极的方法及其结构
公开(公告)号：US06787418B2
公开(公告)日：2004-09-07
申请号：US10355134
申请日：2003-01-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

33. 发明授权

US06902978B2 Method of making the selection gate in a split-gate flash EEPROM cell and its structure 失效
标题翻译：在分闸器快闪EEPROM单元中制作选择栅极的方法及其结构
公开(公告)号：US06902978B2
公开(公告)日：2005-06-07
申请号：US10929396
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

34. 发明申请

US20050029575A1 Method of making the selection gate in a split-gate flash EEPROM cell and its structure 失效
公开(公告)号：US20050029575A1
公开(公告)日：2005-02-10
申请号：US10929396
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.

35. 发明申请

US20050026368A1 Method of making the selection gate in a split-gate flash EEPROM cell its and structure 失效
标题翻译：在分闸器快闪EEPROM单元中选择栅极的方法和结构
公开(公告)号：US20050026368A1
公开(公告)日：2005-02-03
申请号：US10929397
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

36. 发明授权

US06982458B2 Method of making the selection gate in a split-gate flash EEPROM cell and its structure 失效
标题翻译：在分闸器快闪EEPROM单元中制作选择栅极的方法及其结构
公开(公告)号：US06982458B2
公开(公告)日：2006-01-03
申请号：US10929397
申请日：2004-08-31
申请人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
发明人： Wen-Ting Chu , Jack Yeh , Chrong-Jung Lin
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66553 , H01L29/7885
摘要： A method of making the selection gate in a split-gate flash EEPROM cell forms a selection gate on a trench sidewall of a semiconductor substrate to minimize the sidewise dimension of the selection gate and to maintain the channel length. The disclosed method includes the steps of: forming a trench on a semiconductor substrate on one side of a suspending gate structure; forming an inter polysilicon dielectric layer on the sidewall of the suspending gate structure and the trench; and forming a polysilicon spacer on the inter polysilicon dielectric layer as the selection gate. Such a split-gate flash EEPROM cell can produce ballistic hot electrons, improving the data writing efficiency and lowering the writing voltage.
摘要翻译：在分裂栅极快闪EEPROM单元中形成选择栅极的方法在半导体衬底的沟槽侧壁上形成选择栅极，以最小化选择栅极的侧向尺寸并保持沟道长度。所公开的方法包括以下步骤：在悬挂栅结构的一侧上的半导体衬底上形成沟槽; 在悬挂栅结构和沟槽的侧壁上形成多晶硅间介质层; 以及在多晶硅间介质层上形成多晶硅间隔物作为选择栅极。这种分裂栅极快速EEPROM电池可以产生弹道热电子，提高数据写入效率并降低写入电压。

37. 发明授权

US08896096B2 Process-compatible decoupling capacitor and method for making the same 有权
标题翻译：过程兼容去耦电容及其制作方法
公开(公告)号：US08896096B2
公开(公告)日：2014-11-25
申请号：US13553086
申请日：2012-07-19
申请人： Kuo-Chi Tu , Wen-Ting Chu
发明人： Kuo-Chi Tu , Wen-Ting Chu
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L27/2436 , H01L28/40 , H01L29/94 , H01L45/04 , H01L2924/0002 , H01L2924/00
摘要： Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.
摘要翻译：提供去耦电容器件。去耦电容器装置包括在沉积工艺中沉积的第一电介质层部分，其沉积用于非易失性存储单元的第二电介质层部分。使用单个掩模对两个部分进行图案化。还提供了片上系统（SOC）器件，SOC包括位于单个金属间介电层中的RRAM单元和去耦电容器。还提供了一种形成工艺兼容去耦电容器的方法。该方法包括图案化顶部电极层，绝缘层和底部电极层，以形成非易失性存储元件和去耦电容器。

38. 发明授权

US07227218B2 Method and system for forming source regions in memory devices 有权
标题翻译：用于在存储器件中形成源区的方法和系统
公开(公告)号：US07227218B2
公开(公告)日：2007-06-05
申请号：US11094035
申请日：2005-03-30
申请人： Yi-Shing Chang , Wen-Ting Chu
发明人： Yi-Shing Chang , Wen-Ting Chu
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.
摘要翻译：公开了一种存储器件及其制造方法。该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层，浮置栅极层上的第二氧化物层，其中第二氧化物层和浮动栅极层具有第一开口和第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二氧化物层下方被水平地拉回。源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口，其中第三氧化物具有到达源极区域的一部分的第三开口。此外，控制门材料填充在第三开口中。

39. 发明申请

US20070120172A1 Logic compatible non-volatile memory cell 有权
标题翻译：逻辑兼容的非易失性存储单元
公开(公告)号：US20070120172A1
公开(公告)日：2007-05-31
申请号：US11248357
申请日：2005-10-12
申请人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
发明人： Te-Hsun Hsu , Hung-Cheng Sung , Wen-Ting Chu , Shih-Wei Wang
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558
摘要： A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.
摘要翻译：提供了一种非易失性存储单元及其制造方法。非易失性存储单元包括半导体衬底，半导体衬底上的浮置栅极，第一，第二和第三电容器，每个电容器具有第一板并且共用公共浮置栅极作为第二板。非易失性存储单元还包括与第一电容器串联连接的晶体管。晶体管的栅电极连接到存储器阵列的字线，源极/漏极区连接到位线。

40. 发明授权

US06890821B2 Method and system for forming source regions in memory devices 失效
公开(公告)号：US06890821B2
公开(公告)日：2005-05-10
申请号：US10617470
申请日：2003-07-11
申请人： Yi-Shing Chang , Wen-Ting Chu
发明人： Yi-Shing Chang , Wen-Ting Chu
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式