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1. 发明授权

US6110782A Method to combine high voltage device and salicide process 有权
标题翻译：高压装置与自动化处理相结合的方法
公开(公告)号：US6110782A
公开(公告)日：2000-08-29
申请号：US195651
申请日：1998-11-19
申请人： Wen-Ting Chu , Chuan-Li Chang , Ming-Chon Ho , Chang-Song Lin , Di-Son Kwo
发明人： Wen-Ting Chu , Chuan-Li Chang , Ming-Chon Ho , Chang-Song Lin , Di-Son Kwo
IPC分类号： H01L21/8234 , H01L21/8247
CPC分类号： H01L27/11526 , H01L21/823462 , H01L27/11541
摘要： A method for integrating salicide and high voltage device processes in the fabrication of high and low voltage devices on a single wafer is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating a low voltage device area from a high voltage device area. A gate oxide layer is grown in the device areas. A polysilicon layer is deposited overlying the gate oxide layer and isolation areas. A first photomask is formed over a portion of the high voltage device area wherein the first photomask also completely covers the low voltage device area. The polysilicon layer is etched away where it is not covered by the photomask to form a high voltage device. Ions are implanted to form lightly doped source and drain regions within the semiconductor substrate adjacent to the high voltage device wherein the first photomask protects the polysilicon layer in the low voltage device area from the ions. The first photomask is removed. A second photomask is formed over a portion of the low voltage device area where a gate electrode is to be formed wherein the second photomask also completely covers the high voltage device area. The polysilicon layer not covered by the second photomask is etched away to form the gate electrode. The second photomask is removed. The low voltage and high voltage area devices are silicided and the fabrication of the integrated circuit device is completed.
摘要翻译：描述了在单个晶片上制造高电压和低压器件中的自对准硅化物和高电压器件工艺的集成方法。在半导体衬底上形成隔离区域，该半导体衬底围绕低电压器件区域和高电压器件区域电隔离。在器件区域中生长栅极氧化物层。沉积覆盖栅极氧化物层和隔离区的多晶硅层。第一光掩模形成在高电压器件区域的一部分上，其中第一光掩模也完全覆盖低电压器件区域。多晶硅层被蚀刻掉，其未被光掩模覆盖以形成高压器件。植入离子以在与高压器件相邻的半导体衬底内形成轻掺杂的源极和漏极区，其中第一光掩模保护低电压器件区域中的多晶硅层与离子。第一个光掩模被删除。第二光掩模形成在要形成栅电极的低电压器件区域的一部分上，其中第二光掩模也完全覆盖高电压器件区域。蚀刻掉未被第二光掩模覆盖的多晶硅层以形成栅电极。第二个光掩模被删除。低电压和高电压区域的器件被硅化，并且完成了集成电路器件的制造。

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